73m2921 ETC-unknow, 73m2921 Datasheet
73m2921
Related parts for 73m2921
73m2921 Summary of contents
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... The 73M2921 provides DTMF tone generation and detection, precise call progress detect and ADSI functions such as CAS tone detection. Other features include a parallel interface control port between the host processor and the 73M2921. A synchronous serial data synchronizing clocks RXCLK and TXCLK from the modem pump to the controller ...
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... Advanced Single Chip Modem UA[0-1] P UD[0-7] PORT , READ THE MAILBOX PWR UP POWER UP RESET CLK CTRL XTALI CLOCKS XTALO MICCLK RXD Page PWR UP CLK CNTRL CR0 MAILBOX DSP SERIAL DATA INTERRUPTS 14.4 KHz Samples TIMER (MODULATOR & DECIMATOR) SERIAL CLOCKS TXD TXCLK RXCLK ...
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... XTALI and proper loading capacitors, these pins include an inverter for use with parallel resonant mode crystals. MICROCONTROLLER CLOCK: Programmable clock output for use when the system oscillator is on the 73M2921. May be used to drive the system controller. The output frequency is controlled by CR0 bits D11- D9 (MCLK [2:0]). ...
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... Requires a 50K external pull up. WAKE: Active Low Output. Indicates that a power up pin ( ) has been activated when the 73M2921 is in slave mode. The latched signal remains true until a reset of the wake function by a write to CR0 LSByte chip reset. Requires a 50K DESCRIPTION CHIP SELECT: Active Low Input ...
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... HARDWARE REQUIREMENTS The 73M2921 chip is designed for a single +3 Volt supply and for minimum power consumption (~100mW @ 3.3V). It supports power down (idle) mode via microcontroller software control. It will also accept a request for power down from the DTE via hardware control. The device operates from internal ROM/RAM, but may be configured for external ROM operation and external RAM access (for custom applications) using either the prototype or the production packages ...
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... Chip Modem POWER CONTROL The power control circuit determines the state of the 73M2921 when powered down, and the means for waking up the chip. The function is related to the chip and DSP reset functions and is controlled by various input pins and register bits. The chip pins are function are RSTCHIP, RSTDSPB, ENOSC, ENDSPCK, ENMCLK, and PSDIS (1:0) ...
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... Powerup input to active state Powerup input to inactive state DCE-DTE INTERFACE The 73M2921 is designed to interface with a synchronous port such as that found on the TDK 73M2910. It also provides a parallel control interface. This parallel interface appears bit memory mapped peripheral to the host controller. SERIAL DATA INTERFACE The serial data interface is a four pin bi-directional port ...
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... The host controller initiates all communications over the data bus by sending a command to either read or write to a location. CR0 is a special case in that it is accessed directly by way of the address bits and does not generate a response from the 73M2921. All other registers are accessed indirectly by way of a “mailbox” register and will generate a response from the 73M2921. ...
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... A logical 1 on PSDIS[1] masks PSDIS[0] masks Resets the state of the 73M2921 putting it into a known state. The function of this bit is similar to that of the RESET pin, except that this bit does NOT change the setting of the POWERUP SOURCE DISABLE bits. See Table 2. ...
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... The C reads the MSB first, then the LSB. Reading the LSB sets internal mail full flag bit, allowing the 73M2921 to write new data to the mailbox. Mailbox data is not explicitly formatted. The microcontroller and 73M2921 firmware define the control exchange format. ...
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... The Host writes to the Mailbox Data byte (at UA address 11b, write either B0h to access CR1 or D0h to access CR2). Order is important as the writing of the Data byte triggers an internal interrupt in the DSP indicating that new mail is present. The 73M2921 will respond through the mailbox. The contents of the response are not important to the host. ...
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... The response from the 73M2921 will not be defined. The word size transfer of CR1 data is also shown in figure 3. The MS byte is 90h. This enables the digital portion of the 73M2921. The LS byte is 0h. Refer to the configuration register description on pages 10 and 11 for further information. Page ...
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... SLAVE SYNC DESCRIPTION Always 0 DIAGNOSTIC MODE: Must be zero. Always 0 Must be zero. This is a logical 1 if the power supply to the 73M2921 is in the 5V range. Note, this signal is valid only when EN ANALOG (CR2: D10) is enabled. Not Used High Volume 1 0 Medium Volume ...
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... N/A D15 Wide Transmit Bandwidth (3) GENERAL REGISTER ACCESS (GRA) For General Register Access (GRA), the mailbox the Control byte from the host controller is broken down into bit segments as follows: General Register Access Control Byte: Microcontroller to 73M2921 BIT 7 BIT 6 Res WT Res = Reserved WT/ = Word Transfer/Byte Transfer ...
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... Lowers to interrupt the C indicating that data is in the Mailbox from the 73M2921. The response from the 73M2921 can either be polled by the host controller or interrupt-driven. In the interrupt- driven response, an interrupt is issued by the 73M2921 from time the microcontroller reads two bytes (Control, Data) from the 73M2921. Reading valid Data clears the interrupt for the next command ...
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... An example of a write cycle is shown in Figure 4 and 5. Figure 4 shows the activity on the interface data pins and . First there are two command bytes sent by the host controller, then an interrupt is generated in telling the host to read the response data, then the controller reads back the response from the 73M2921. The interrupt is reset when the LS byte is read. ...
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... Control byte to determine whether the interrupt was the result of a GRA in progress or an Unsolicited Response from the General register set status registers. An Unsolicited Response must always be serviced first, then the GRA in progress can be resumed. The data received from the 73M2921 is broken into Control and Data fields. Address 10b is the Control byte and Address 11b is the Data byte. ...
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... Selects answer/originate and retrain modes allowed 06h Selects test patterns, test mode handshaking, scrambler/descrambler operation. 07h Read only, revision level of the 73M2921 08h Enables interrupts on changes of state from Detect Reg. 1 status bits. 09h Read only, indicates status of detectors used during handshaking for various modes ...
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... Informs processor of a successful V.21 connection. Fax Mode Informs processor of a successful V.21 CH2 connection. Data Mode Informs processor of a successful V.23 connection. Fax Mode Informs processor of a successful V.29 connection. TDK Semiconductor 73M2921 Advanced Single Chip Modem BIT D2 BIT D1 V.22bis Bell 202 BIT D3 BIT D2 BIT D1 V ...
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... Advanced Single Chip Modem DTMF DIAL REGISTER BIT D7 BIT D6 BIT D5 RES TWIST2 TWIST1 BIT NO. NAME D3, D2, D1, D0 DTMF 3-0 Digit Twist 2-0 D7 Reserved The TXDT BIT 3 of the TRANSMIT CONTROL REGISTER (0Ch) must be set for DTMF tone transmission. TXDT is gated on and off during the transmission of tones when dialing DTMF digits ...
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... Reserved for future use 1 Indicates a valid DTMF detection 0 Indicates no detect for polled applications TDK Semiconductor 73M2921 Advanced Single Chip Modem MODE: CALL PROGRESS BIT D2 BIT D1 BIT D0 DTDET DTDET DTDET 2 1 DESCRIPTION Detects 697 Hz & 1209 Hz Detects 697 Hz & 1336 Hz Detects 697 Hz & ...
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... When Modulation is set for Bell 202, the 73M2921 transmits @ 1200 bps. Sets the modem into Originate mode. When 0 Modulation is set for V.23, the 73M2921 receives in main channel @ 1200 bps and Transmits in back channel @ 75 bps. When Modulation is set for Bell 202, the 73M2921 receives at 1200 bps. ...
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... ADDRESS: 07h (07d, 00111b) BIT D4 BIT TDK Semiconductor 73M2921 Advanced Single Chip Modem MODE: DATA* BIT D2 BIT D1 BIT D0 SDP2 SDP1 SDP0 DESCRIPTION Send Data Send Marks Send Space Send Dotting Pattern (Not valid for FSK) ...
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... Valid in Data Mode This bit will be set if a handshake is currently in progress. This bit is cleared by the 73M2921 when either a handshake has been successful and the 73M2921 has entered DATA mode, or when a handshake has been aborted and the 73M2921 is placed into IDLE mode. ...
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... This bit will be set if V.21 channel 2 tone is detected. Progress Modes Originate Only Valid in Call This bit will be set if the 2250Hz component of S0 Progress Modes (unscrambled mark) is detected. Originate Only TDK Semiconductor 73M2921 Advanced Single Chip Modem MODE: SEE DET REG 2 BIT D2 BIT D1 BIT D0 1300Hz RES. ...
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... Advanced Single Chip Modem TRANSMIT CONTROL REGISTER BIT D7 BIT D6 BIT D5 TXEN Res. Res. NAME D0, D1,D2 Modulation Type D3 Transmit DTMF Tones D4,D5,D6 Reserved D7 Master Transmit Enable Page ADDRESS: 0Ch (012d, 01100b) BIT D4 BIT D3 Res. TXDT CONDITION DESCRIPTION Valid in Data Modes ...
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... Reserved Reserved Reserved - Reserved for future use TDK Semiconductor 73M2921 Advanced Single Chip Modem MODE: ALL MODES BIT D2 BIT D1 BIT D0 TXAT2 TXAT1 TXAT0 Page ...
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... Advanced Single Chip Modem FAX HANDSHAKE REGISTER BIT D7 BIT D6 BIT D5 T/ Res. BIT NO. NAME D0, D1,D2, D3 Fax Connect Mode D4,D5,D6 Reserved D7 Transmit Page ADDRESS: E0h (014d, 01110b) BIT D4 BIT D3 Res. Res. FM3 CONDITION DESCRIPTION Defines Modulation for transmit or receive ...
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... Forces a hard initialization of all state machine timing and control variables. Allows normal operation. 0 Reserved Allows normal operation. Valid for V.22 and V.22 bis only 0 TDK Semiconductor 73M2921 Advanced Single Chip Modem MODE: ALL MODES BIT D2 BIT D1 BIT D0 FAX DATA CP Page ...
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... Advanced Single Chip Modem MSE0 REGISTER (LSB) BIT D7 BIT D6 BIT D5 This register returns the Least Significant Byte of the Mean Squared Error number from the DSP. Used to determine Signal Quality. MSE1 REGISTER (MSB) BIT D7 BIT D6 BIT D5 This register returns the Most Significant Byte of the Mean Squared Error number from the DSP. Used to determine Signal Quality ...
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... Indicates detection of 620 Hz tone 1 Indicates detection of 2130 Hz tone (component of CAS tone) 1 Indicates detection of 2750 Hz tone (component of CAS tone) - Reserved for future use TDK Semiconductor 73M2921 Advanced Single Chip Modem MODE: CALL PROG. BIT D2 BIT D1 MODE: CALL PROG. ORIGINATE ONLY BIT D2 BIT D1 480 Hz ...
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... Advanced Single Chip Modem ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Operation outside these rating limits may cause permanent damage to this device. PARAMETER VDD Supply Voltage Storage Temperature Applied Voltage Note: All inputs and outputs are protected from static charge using built-in, industry standard protection devices and all outputs are short- circuit protected ...
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... Vref = 1.25V) ANSWER TONE GENERATOR (2100 or 2225 Hz) Output Amplitude Output Distortion February 99 Rev M MIN 1.1 pk-pk ( VDD 5V max CONDITION Vcc = 5V Distortion products in receive band TDK Semiconductor 73M2921 Advanced Single Chip Modem NOM MAX UNIT 1.25 1.25 1.4 MIN NOM MAX 50 -100 0 100 -0 ...
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... Advanced Single Chip Modem 6 DTMF GENERATOR Frequency Accuracy Output Amplitude Low Band Output Amplitude High Band Twist IMPRECISE CALL PROGRESS DETECTOR Detect Level Reject Level Delay Time Hold Time CARRIER DETECT Threshold Hysteresis Delay Time All Modes Hold Time All Modes ...
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... Guard Tones Off 10 kHz, Guard Tones Off 12 kHz, Guard Tones Off CONDITION 550 Hz 1800 Hz 550 Hz and 1800Hz Low High High Table Parallel Interface Timing TDK Semiconductor 73M2921 Advanced Single Chip Modem MIN NOM MAX -35 -55 -65 MIN NOM MAX -4.5 -3 -1.5 -7.5 -6 ...
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... The more digital circuitry present on the PC board, the more attention to noise control is needed. The 73M2921 should be considered a high performance analog device electrolytic capacitor in parallel with a 0.1 F Ceramic capacitor should be placed between VPD and VND as well as between VPA and VNA. A ...
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... February 99 Rev M 1.00E-01 1.00E-02 1.00E-03 1.00E-04 1.00E-05 1.00E-06 -9 -10 -11 -12 -13 -14 -15 -16 -17 -18 SNR (Rx Signal/3k Hz) (dB) FIGURE 9 - 2400 BPS QAM SNR vs. BER TDK Semiconductor 73M2921 Advanced Single Chip Modem Answer Flat Originate Flat Answer 3002 Originate 3002 Page ...
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... Advanced Single Chip Modem 1.00E-01 1.00E-02 1.00E-03 1.00E-04 1.00E-05 1.00E-06 Page 3002 Line -6 -10 -14 -18 -22 -26 -30 -34 -38 -42 2400 BPS QAM Power Input Level Ans./Orig. Mode FIGURE 10 – Power Input Level vs. BER TDK Semiconductor Answer Originate February 99 Rev M ...
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... VND 75-81 n/c 82 VPD 83 n/c 84-90 91 n/c 92-100 TDK Semiconductor 73M2921 Advanced Single Chip Modem Pin Description analog negative input analog positive power supply analog negative power supply speaker driver output microcontroller wake-up output reset chip input transmit serial data input transmit data clock output ...
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... Pin QFP 73M2921-IG TDK Semiconductor CAUTION: Use handling procedures necessary for a static sensitive component. 80 n/c 79 n/c n n/c 76 n/c 75 n/c VND 74 73 MAKE NO CONNECTIONS 72 MAKE NO CONNECTIONS 71 MAKE NO CONNECTIONS 70 MAKE NO CONNECTIONS 69 MAKE NO CONNECTIONS ...
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... TDK Semiconductor Corp., 2642 Michelle Dr., Tustin, CA 92780, (714) 508-8800, FAX (714) 508-8877, http://www.tsc.tdk.com February 99 Rev M 19.62 (0.772) 20.12 (0.792) 23.77 (0.936) 24.03 (0.946) 13.62 (0.536) 14.12 (0.556) 2.6 (0.102) 2.8 (0.110) 0.15 (0.006) 0.50 (0.020) ORDER NUMBER 73M2921-IG TDK Semiconductor 73M2921 Advanced Single Chip Modem 0.70 (0.028) 0.90 (0.035) 17.77 (0.700) 18.03 (0.710) PACKAGING MARK 73M2921-IG Page ...