pex8505 PLX, pex8505 Datasheet

pex8505

Manufacturer Part Number

pex8505

Description

5 Lane, 5 Port Pci Express Switch, 15 X 15mm Pbga

Manufacturer

PLX

Datasheet

1.PEX8505.pdf (4 pages)

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Features

PEX 8505 General Features

o 5-lane PCI Express switch

o Up to five ports (x1, x2)

o 15mm x 15mm, 196-ball PBGA pkg.

o Typical Power: 0.8 Watts

PEX 8505 Key Features

o Standards Compliant

o High Performance

o Flexible Configuration

o PCI Express Power Management

o Quality of Service (QoS)

o Reliability, Availability,

- Gen 1 (2.5Gbps) Integrated

- PCI Express Base Specification, r1.1

- PCI Power Management Interface

- Cut-thru with low packet latency

- Max Payload Size of 1024 Bytes

- Non-blocking internal architecture

- Full line rate on all ports

- Five flexible & configurable ports

- Lane and polarity reversal

- Configurable with strapping pins,

- Link power management states: L0,

- Device states: D0 and D3hot

- One Virtual Channel per port

- Eight Traffic Classes per port

- Weighted Round-Robin Ingress Port

Serviceability

- Three Standard Hot-Plug Controllers

- Transaction layer end-to-end CRC

- Poison bit support

- Basic and Advanced Error Reporting

- Per port error diagnostics

- Fatal Error (FATAL_ERR#) signal

- INTA# signal

- Port status bits

- Eight software controllable General

- JTAG boundary scan

SerDes

Specification r1.2

(x1, x2)

EEPROM, I

L0s, L1, L2/L3 Ready and L3

Arbitration

supporting PCI SHPC spec r1.0

support

• Bad DLLPs

• Bad TLPs

• CRC errors and more

(legacy SERR equivalent)

Purpose Output (GPO) signals

Version 1.2 2008

C or Host software

Low-Power 5-Lane, 5-Port ExpressLane

The PEX 8505 device offers PCI Express switching capability conforming to the

PCI Express Base specification revision 1.1. This device enables users to add

scalable high bandwidth, non-blocking interconnects at the lowest cost to a wide

variety of applications including communications platforms, consumer products,

servers, storage systems, blade servers, industrial systems and embedded-control

products. The PEX 8505 can be used as a fan-out, or peer-to-peer switch, and is

well-suited for Control Plane Applications, I/O Expansion, Video Surveillance,

Systems, Embedded System

Port Configurations

The PEX 8505 offers five lanes and up to five ports supporting x1 and x2 lane

widths. The PEX 8505 features a flexible central packet memory that allocates a

memory buffer for each port as required by the application or endpoint. This buffe

allocation along with the device's flexible packet flow control minimizes

match.

High Performance

The PEX 8505 architecture supports packet cut-thru with low latency (138ns).

This, combined with large packet memory (up to 1024 byte maximum payload

size) and non-blocking internal switch architecture, provides full line rate on all

embedded systems and AMC module

End-to-End Packet Integrity

The PEX 8505 provides end-to-end CRC protection (ECRC) and Poison-bit

support to enable designs that require end-to-end data integrity. These features a

ExpressLane switch product line

Configuration Flexibility

The PEX 8505 provides several ways to configure its operations. The device can be

configured through strapping pins, I

performance monitor

Interoperability

The PEX 8505 is designed to be fully compliant with the PCI-SIG PCI Express base

specification revision 1.1. Additionally, it supports auto-negotiation, lane rever

testing in PLX’s Interoperability Lab.

Low Power with Granular SerDes Control

The PEX 8505 provides low power capability that is fully compliant with the

PCI Express power management specification. For even lower power, the SerDes

physical links can be programmed for desired power or turned off when unused.

nd polarity reversal. The PEX 8505 als

ottlene

orts for performance hungry applications s

ptional in the PCI Express specific

ptional serial EEPROM. This allows for easy debug during the development phase,

Flexible & Versatile PCI Express

ulti-Function Printers, DVRs, Industrial Contr ol Systems, Medical Imaging

cks when the upstream and aggregated downstream bandwidths do not

www.plxtech.com

ing during the operation phase, and driver or software upgrade.

PEX 8505

s and AMC modules.

ation, but PLX provides them across its entire

C interface, CPU configuration cycles, or an

o undergoes thorough Interoperability

uch as docking stations, control planes,

PCIe Switch

Switch

sal,

Related parts for pex8505

pex8505 Summary of contents

Page 1

... The PEX 8505 provides end-to-end CRC protection (ECRC) and Poison-bit support to enable designs that require end-to-end data integrity. These features a o ptional in the PCI Express specific ation, but PLX provides them across its entire ExpressLane switch product line . Configuration Flexibility The PEX 8505 provides several ways to configure its operations ...

Page 2

... The ExpressLane PEX 8505 supports software control of the SerDes outputs to allow optimization of power and signal strength in a system. The PLX SerDes implementation supports four levels of power – off, low, typical, and high. The SerDes block also supports loop-back modes and advanced reporting of error conditions, which enables efficient debug and management of the entire system ...

Page 3

... PCI Express-to-local bus bridges, the PEX 8505 can connect to other embedded devices, such as FPGAs. This allows video capture devices to interface to a PCI Express host taking advantage of the PCI Express performance. For more information on the PCI Express-to-Local Bus bridge, please visit PLX’s website at www.plxtech.com/bridges. CPU CPU CPU Camera ...

Page 4

... PLX Technology, Inc. All rights reserved. PLX and the PLX logo are registered trademarks of PLX Technology, Inc. ExpressLane is a trademark of PLX Technology, Inc., which may be registered in some jurisdiction. All other product names that appear in this material are for identification purposes only and are acknowledged to be trademarks or registered trademarks of their respective companies ...

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