pex-8624 PLX, pex-8624 Datasheet

pex-8624

Manufacturer Part Number

pex-8624

Description

24-lane, 6-port Pci Express Gen 2 5.0 Gt/s Switch, 19 X 19mm Fcbga

Manufacturer

PLX

Datasheet

1.PEX-8624.pdf (4 pages)

Current page: 1 of 4
Download datasheet (214Kb)

Features

o 24-lane, 6-port PCIe Gen 2 switch

o 19 x 19mm

o Typical Power: 3.0 Watts

o Standards Compliant

o High Performance

o Flexible Configuration

o Dual-Host & Fail-Over Support

o Quality of Service (QoS)

o Reliability, Availability, Serviceability

PEX 8624 General Features

PEX 8624 Key Features

- Integrated 5.0 GT/s SerDes

- PCI Express Base Specification, r2.0

- PCI Power Management Spec, r1.2

- Microsoft Vista Compliant

- Supports Access Control Services

- Dynamic link-width control

- Dynamic SerDes speed control

- Non-blocking switch fabric

- Full line rate on all ports

- Packet Cut-Thru with 160ns max packet

- 2KB Max Payload Size

- Read Pacing (bandwidth throttling)

- Dual cast

- Ports configurable as x1, x2, x4, x8

- Registers configurable with strapping

- Lane and polarity reversal

- Compatible with PCIe 1.0a PM

- Configurable Non-Transparent port

- Moveable upstream port

- Crosslink port capability

- Eight traffic classes per port

- Weighted round-robin source

- 3 Hot-Plug Ports with native HP Signals

- All ports Hot-Plug capable thru I

- ECRC and Poison bit support

- Data Path parity

- Memory (RAM) Error Correction

- INTA# and FATAL_ERR# signals

- Advanced Error Reporting

- Port Status bits and GPIO available

- Per port error diagnostics

- Performance Monitoring

- JTAG AC/DC boundary scan

(backwards compatible w/ PCIe r1.0a/1.1)

latency (x8 to x8)

pins, EEPROM, I

port arbitration

(Hot-Plug Controller on every port)

• Per port payload & header counters

Version 0.95 2008

, 324-pin FCBGA package

C, or host software

The ExpressLane

capability enabling users to add scalable high bandwidth, non-blocking

interconnection to a wide variety of applications including

workstations, storage systems, and communications platforms. The

PEX 8624 is well suited for fan-out, aggregation, and peer-to-peer

applications.

High Performance & Low Packet Latency

The PEX 8624 architecture supports packet cut-thru with a maximum

latency of 160ns (x8 to x8). This, combined with large packet memory and

non-blocking internal switch architecture, provides full line rate on all ports

for performance-hungry applications such as servers and switch fabrics.

The low latency enables applications to achieve high throughput and

performance. In addition to low latency, the device supports a max payload

size of 2048 bytes, enabling the user to achieve even higher throughput.

Data Integrity

The PEX 8624 provides end-to-end CRC (ECRC) protection and Poison bit

support to enable designs that require end-to-end data integrity. PLX also

supports data path parity and memory (RAM) error correction as packets

pass through the switch.

Flexible Register & Port Configuration

The PEX 8624’s 6 ports can be configured to lane widths of x1, x2, x4, or

x8. Flexible buffer allocation, along with the device's flexible packet flow

control, maximizes throughput for applications where more traffic flows in

the downstream, rather than upstream, direction. Any port can be designated

as the upstream port, which

can be changed dynamically.

The PEX 8624 also provides

several ways to configure its

registers. The device can be

configured through strapping

pins, I

software, or an optional

serial EEPROM. This allows

for easy debug during the

development phase,

performance monitoring

during the operation phase,

and driver or software

upgrade. Figure 1 shows

some of the PEX 8624’s

common port configurations.

PCIe Gen 2, 5.0GT/s 24-

C interface, host

PEX 8624

PEX 8624 device offers PCI Express switching

Figure 1. Common Port Configurations

PEX 8624

lane, 6-

5 x4

x4 x4

port Switch

PEX 8624

x4 x4 x4

Related parts for pex-8624

pex-8624 Summary of contents

Page 1

... Flexible Register & Port Configuration The PEX 8624’s 6 ports can be configured to lane widths of x1, x2, x4, or x8. Flexible buffer allocation, along with the device's flexible packet flow control, maximizes throughput for applications where more traffic flows in the downstream, rather than upstream, direction ...

Page 2

... Gen 1 endpoints. In Figure 3, the PCIe slots connected to the PEX 8624’s downstream ports can be populated with either PCIe Gen 1 or PCIe Gen 2 devices. Conversely, the PEX 8624 can also be used to create Gen 2 ports on a Gen 1 native Chip Set in the same fashion. C interface. ...

Page 3

... Advanced Mezzanine Cards (AMC) for I/O expansion. In the example shown below in Figure 4, the PEX 8624 is used on a Quad-Port Network Interface Card (NIC AMC form factor. The PEX 8624 uses a x8 upstream link to the host and four x4 downstream links to to fan- out to the four MAC/PHY controllers. ...

Page 4

... The PEX 8624RDK is a hardware module containing the PEX 8624 which plugs right into your system. The PEX 8624RDK can be used to test and validate customer software, or used as an evaluation vehicle for PEX 8624 features and benefits. The PEX 8624RDK provides everything that a user needs to get their hardware and software development started ...

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