en5330 Enpirion, en5330 Datasheet - Page 9

• Manufacturer Part Number: en5330
• Description: 3a Voltage Mode Synchronous Buck Pwm Dc-dc Converter With Integrated Inductor
• Manufacturer: Enpirion

July 2007
voltage condition the POK signal will go low and
will remain in this condition until the output
voltage has dropped to 95% of the programmed
output voltage before returning to the high state
(see also Over Voltage Protection).
Over-Current Protection
The cycle-by-cycle current limit function is
achieved by sensing the current flowing through
the sense P-MOSFET and a signal generated by
a differential amplifier with a preset over-current
threshold. During a particular cycle, if the over-
current threshold is exceeded, the power P-
MOSFET and N-MOSFET are turned off. If the
over-current condition is removed, the over-
current protection circuit will enable the PWM
operation. If the over-current condition persists,
the converter will eventually go through a full
soft-start cycle. This circuit is designed to provide
high noise immunity.
Over-Voltage Protection
When the output voltage exceeds 120% of the
programmed output voltage, the PWM operation
stops, the lower N-MOSFET is turned on and the
POK signal goes low. When the output voltage
drops below 95% of the programmed output
voltage, normal PWM operation resumes and
POK returns to its high state. If the condition
persists, the device will go through a soft-start
cycle.
Thermal Overload Protection
Thermal shutdown will disable operation once
the Junction temperature exceeds approximately
160ºC. Once the junction temperature drops by
approx 20ºC, the converter will re-start with a
normal soft-start.
Low Input Voltage Operation
Circuitry is provided to ensure that when the
input voltage is below the specified voltage
range, the operation of the converter is controlled
and predictable. Circuits for hysteresis, input de-
glitch and output leading edge blanking are
included to ensure high noise immunity and
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9
prevent false tripping.
Compensation
The EN5330 is internally compensated through
the use of a type 3 compensation network and is
optimized for use with about 50µF of output
capacitance and will provide excellent loop
bandwidth and transient performance for most
applications. (See the section on Capacitor
Selection for details on required capacitor types.)
In some cases modifications to the compensation
may be required. For more information, contact
Enpirion Applications Engineering support.
Layout Considerations
The EN5330 Layout Guidelines application note
provides
recommendations for this part. The following are
general layout guidelines to consider.
The CMOS chip inside the EN5330 has two
grounds: AGND for the controller, and PGND for
the power stage. These two grounds need to be
connected outside the package at one point
through a low-impedance trace. The connection
should be made such that the impedance
between the connection point and the AGND pad
on the package is minimized. Since the internal
voltage sensing circuit is based on AGND, the
connection of the two grounds should also be
made such that the best voltage regulation can
be achieved. The soft-start capacitor, the voltage
programming resistors, and any other external
control component should be tied to AGND.
The placement of the input decoupling capacitors
between PVIN and PGND is very critical. These
components should be placed such that they
have the lowest inductance traces to PVIN and
PGND.
There are two thermal pads underneath the
device. The centrally located pad is PGND, and,
depending on the number of layers of the PC
board, it needs to be connected to a thermal
plane in order to conduct heat away from the
device. Note that if any of the thermal planes is
also connected to AGND, the impedance
more
details
on
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specific
layout