ncs5021 ON Semiconductor, ncs5021 Datasheet

no-image

ncs5021

Manufacturer Part Number
ncs5021
Description
Dual Band Edge Compatible Pa Controller
Manufacturer
ON Semiconductor
Datasheet
NCS5021
Product Preview
Dual Band EDGE
Compatible PA Controller
GSM and DCS standards. It significantly reduces the number of
external passive devices while giving the RF designer the capability to
perfectly tune the control loop. This device is compatible with both
constant and non−constant envelope modulations, which are used with
GSM and GSM/EDGE.
Features
Typical Applications
RF GSM
RF GND
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
RF DCS
© Semiconductor Components Industries, LLC, 2006
July, 2006 − Rev. 6
RAMP
CTRL
The NCS5021 circuit is dedicated to RF Power amplifier control for
Integrated Two 50 W Matched RF Power Detectors
Direct Supply from Battery Voltage
Low Bandwidth Mode (EDGE)
High Gain Integrator Requesting only One External Capacitor
PA Control Buffer Compatible with Gate Controlled Amplifiers
Generation of Pre−bias Level for PA at Start of Burst
12 Pins QFN 3 x 3
Global System for Mobile Communication (GSM/DCS)
Personal Communication Network (PCN)
10
12
11
9
CMOS DETECTOR
BAND SELECT
50
50
100 kHz
2
W
W
Figure 1. Functional Block Diagram
75 mV
4
GND
+
V
CC
+
8
SELECT
EDGE
CEXT
1
1/100
1/1
3
PRESET
7
V
+
MIN
Calibration
Timer
G = 2
Clamp
1
ENABLE
5
250 k
6
V
APC
NCS5021MN
NCS5021MNR2
QFN 3x3−12 LEAD
RF GSM
RF GND
RF DCS
Device
SQL SUFFIX
CASE 485N
1
xxx
Code
A
L
Y
W
ORDERING INFORMATION
QFN3x3−12 (Top View)
http://onsemi.com
10
11
12
= Specific Device
= Assembly Location
= Wafer Lot
= Year
= Work Week
QFN3x3−12
QFN3x3−12
9
1
Package
Publication Order Number:
2
8
7
3
12
Bulk/Railed/Tray
6
5
4
Tape & Reel
MARKING
DIAGRAM
1
V
ENABLE
GND
Shipping
APC
NCS5021/D
ALYW
xxx

Related parts for ncs5021

ncs5021 Summary of contents

Page 1

... Product Preview Dual Band EDGE Compatible PA Controller The NCS5021 circuit is dedicated to RF Power amplifier control for GSM and DCS standards. It significantly reduces the number of external passive devices while giving the RF designer the capability to perfectly tune the control loop. This device is compatible with both constant and non− ...

Page 2

... BAND GND CEXT SELECT http://onsemi.com 2 GSM −18 dB DCS −14 dB NCS5021 V 6 APC Clamp Calibration 250 k Timer 5 ENABLE V PRESET MIN V REF GSM −18 dB −14 dB DCS NCS5021 V 6 APC Clamp Calibration 250 k Timer 5 ENABLE V PRESET MIN V REF ...

Page 3

PIN DESCRIPTION Pin Name 1 CEXT Integrator’s external capacitor: The external capacitor is determining the integrator’s frequency response and has a direct impact over the loop stability and its transient response. 2 BAND SELECT GSM/DCS band selection: A logical “0” ...

Page 4

ELECTRICAL CHARACTERISTICS Limits apply for TA between −30°C to +85°C (unless otherwise noted). Input Specifications Pin Rating 8 Operating Power Supply (Note 6) 8 Active Mode Current Consumption (Unloaded) (Note 6) 8 Power Down Current Consumption (Note 6) 5 Wake ...

Page 5

ELECTRICAL CHARACTERISTICS Limits apply for TA between −30°C to +85°C (unless otherwise noted). Integrator Section Pin Rating − DC Gain (Note 11) Open Loop Band−Width from the Detector (RF GSM or RF DCS) to Output Buffer ( ...

Page 6

TYPICAL PERFORMANCE CHARACTERISTICS 80 60 EDGE = −20 EDGE = 1 −40 −60 10 100 1 FREQUENCY (Hz) Figure 4. Open−Loop Gain at CEXT = 1.0 nF 180 EDGE = 0 135 90 ...

Page 7

TYPICAL PERFORMANCE CHARACTERISTICS 2 −30° −1 +85°C −2 − OUTPUT (dBm) Figure 10. PA Output Drift vs. Temperature with 18 dB Coupler at 900 MHz ...

Page 8

TYPICAL PERFORMANCE CHARACTERISTICS −20 −30 H2 −40 −50 H3 −60 −70 −80 −90 −100 −20 −10 0 INPUT POWER (dBm) Figure 16. Return Harmonic by Input RF GSM or RF DCS at 900 MHz 2.4 2.2 2 1.8 1.6 1.4 ...

Page 9

V ENABLE Pin 4 V BAND SELECT Pin 3 V RAMP CTRL Pin 11 100 EDGE SELECT Pin 2 V VAPC Pin 7 dBc + Nominal Level −1 −6 −15 −30 dBc RF Power Level ...

Page 10

... Power−down Mode During the unused time slots in Time Division Multiple Access (TDMA) systems, the NCS5021 must be in low power mode by applying a zero logic level on pin ENABLE. This function saves power from battery and put PA in low power by supplying very low level to output buffer V Also when power− ...

Page 11

... R1 100 Figure 21. Demo Board Schematic DEMO BOARD MIN 3 RAMP C 5 ENABLE 7 EDGE S 9 SYNCHRO 11 V APCG 13 15 NCS5021QFN12 10 RF GSM 11 AGND 12 RF DCS TP1V CC V CONTROL TP2 RAMP C RAMP C TP4 ENABLE V CONTROL ENABLE J1 1 ...

Page 12

DEMO BOARD Figure 23. PCB Top View Figure 24. PCB Bottom View http://onsemi.com 12 ...

Page 13

... COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS DIM MIN MAX A 0.80 1.00 A1 0.00 0.05 A2 0.65 0.75 A3 0.20 REF b 0.20 0.30 D 3.00 BSC D2 1.50 1.80 E 3.00 BSC E2 1.50 1.80 e 0.50 BSC K 0.20 −−− L 0.35 0.45 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NCS5021/D ...

Related keywords