rt9244 Richtek Technology Corporation, rt9244 Datasheet - Page 10

• Manufacturer Part Number: rt9244
• Description: Multi-phase Controller Core Power Supply
• Manufacturer: Richtek Technology Corporation

RT9244
The sensing circuit gets
R
input bias current. I
side MOSFET turns off (See Figure 2). Therefore,
DAC Offset Voltage & Droop Tuning
The DAC output voltage decreases by V
V
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10
The DAC offset voltage is set by compensation network
& VOSS pin external resistors by
The S/H current signals from power channels are injected
to ADJ pin to create droop voltage.
I
I
T
I
X
X
VOSS
CORE
SP
OFF
Figure 3. DAC Offset Voltage & Droop Tune Circuit
(S/H)
(S/H)
= R
=
PWM Signal & High Side MOSFET Gate Signal
R
=
Figure 2. Inductor Current and PWM Signal
load droop (see Figure 3).
SN
=
=
1
VOSS
V
⎡
⎢
⎣
I
⎡
⎢
⎢
⎢
⎢
⎣
Current
Source
to cancel the voltage drop caused by GM amplifier
L
V
I
Low Side MOSFET Gate Signal
L(AVG)
(S/H)
IN
R
V
V
R
Falling Slope = Vo/L
COMP
OSS
−
VOSS
SP
IN
×
Inductor Current
V
−
R
O
X
1
S
4
V
⎤
⎥
⎦
is sampled and held just before low
EA
I
VOSS
I ,
×
>
O
+
-
L
−
5uS
V
(S/H)
+
I
CORE
-
X
⎡
⎢
⎣
V
=
FB
R
F1
=
IN
I
for
L
V
R
×
2L
−
I
IN
SP
+
L
R
V
fosc
V
(AVG)
V
S
-
⎛
⎜
⎝
V
ADJ
ADJ
O
DAC
R
⎤
⎥
⎦
by local feedback.
R
VOSS
1
ADJ
I
×
=
ADJ
−
L(S/H)
V
=
R
ADJ
∑
I
5uS
L
V
ADJ
200kHz
L
O
⎞
⎟
⎠
to form the
×
×
×
⎤
⎥
⎥
⎥
⎥
⎦
∑
R
T
4
×
1 f
I 2
OFF
2
I
2I
2I
2I
2I
R
L(AVG)
R
X
X1
X2
X3
X4
SP
S
,
.
Protection and SS Function
For OVP, the RT9244 detects the V
of the differential amplifier output. Eliminate the delay due
to compensation network (compared to sensing FB voltage)
for fast and accurate detection. The trip point of OVP is
140% of normal output level. The PWM outputs are pulled
low to turn on the low side MOSFET and turn off the high
side MOSFET of the synchronous rectifier at OVP. The
OVP latch can only be reset by V
on reset sequence. The PGOOD detection trip point of
V
open drain output pulls low when V
trip point. For V
(VCC & DVD are lower than trip point or OVP) reset the
output low.
Soft-start circuit generates a ramp voltage by charging
external capacitor with 13μA current after IC POR acts.
The PWM pulse width and V
ramp to reduce the inrush current and protect the power
devices.
Over-current protection trip point is internally set at around
100μA for each channel. OCP is triggered if one channel
S/H current signal I
PWM output latched at high impedance to turn off both
high and low side MOSFETs in the power stage and initial
the hiccup mode protection. The SS pin voltage is pulled
low with a 13μA current after it is less than 90% V
converter restarts after SS pin voltage < 0.2V. Three times
of OCP disable the converter and only release the latch by
POR acts (see Figure 4).
CORE
V
I
LOAD
CORE
S.S
0A
0V
is 92% lower than the normal level. The PGOOD
COUNT = 1 COUNT = 2 COUNT = 3
Count = 1
ID
T0,T1
jumping issue, only power fail conditions
X
>
Count = 2
⎛
⎜
⎝
Overload
Figure 4.
Applied
0
T2
9K
6 .
CORE
TIME
TIME
V
⎞
⎟
⎠
DS9244-06 March 2007
are clamped by the rising
×
CC
CORE
Count = 3
. 1
T3,T4
CORE
or DVD restart power
. 5
by V
Controller forces
is lower than the
DIF
pin voltage
CC
. The