rt9259a Richtek Technology Corporation, rt9259a Datasheet - Page 10

• Manufacturer Part Number: rt9259a
• Description: Synchronous Buck Dc-dc Linear Power Controller
• Manufacturer: Richtek Technology Corporation

(500mV/Div)
(500mV/Div)
RT_DIS
RT9259A
Soft Start for Synchronous Buck Converter
A built-in soft-start is used to prevent surge current from
power supply input during power on (referring to the
Functional Block Diagram). The error amplifier EA is a three-
input device. SSE or V
the behavior
voltage SSE linearly ramps up to about 4V after VIN1
existence is recognized with about 2ms delay.
the output voltage ramps up smoothly to its target level.
The rise time of output voltage is about 2ms as shown in
Figure 3. V
V
SSE is also used for LDO soft start. LDO input voltage
VIN2 MUST be ready before SSE starts to ramp up.
Otherwise UVP function of LDO may be triggered and shut
down the RT9259A.
Under Voltage Protection
The voltages at FB and FBL pin are monitored for under
voltage protection (UVP) after the soft start is completed.
UVP is triggered if one of the feedback voltages is under
(50% x V
the RT9259A PWM controller is shut down when V
lower than the UVP threshold. In Figure 5, the RT9259A
shuts down after 4 time UVP hiccups triggered by FBL.
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10
(20V/Div)
V
(10V/Div)
REF1
UGATE
LGATE
OUT1
.
REFX
REF1
Figure 3 : Start up by RT_DIS
non-inverting input. The internal soft start
) with a 30us delay. As shown in Figure 4,
takes over the behavior EA when SSE >
REF1
whichever is smaller dominates
Time (1ms/Div)
According,
FB
drops
(500mV/Div)
(500mV/Div)
Over Current Protection
The RT9259A senses the current flowing through lower
MOSFET for over current protection (OCP) by sensing the
PHASE pin voltage as shown in the Functional Block
Diagram. A 40uA current source flows through the external
resistor R
across the resistor. OCP is triggered if the voltage at
PHASE pin (drop of lower MOSFET V
0.4V when low side MOSFET conducting. Accordingly
inductor current threshold for OCP is a function of
conducting resistance of lower MOSFET R
I
(20V/Div)
(20V/Div)
COMP
OCSET
(10V/Div)
(20V/Div)
UGATE
UGATE
FB
LGATE
(1V/Div)
V
V
OUT
OUT1
Figure 5. UVP hiccups triggered by FBL
=
OCSET
40
Figure 4. UVP triggered by FB
μ
A
to PHASE pin causes 0.8V voltage drop
×
R
R
DS(ON)
OCSET
Time (10ms/Div)
Time (10ms/Div)
-
0.4V
DS9259A-02 March 2007
DS
) is lower than −
V
IN1
DS(ON)
= 12V to 0V
V
IN2
as :
= 0V