rt9210 Richtek Technology Corporation, rt9210 Datasheet - Page 14

• Manufacturer Part Number: rt9210
• Description: Dual Synchronous Buck Dc-dc Controller Memory Vddq Termination
• Manufacturer: Richtek Technology Corporation

RT9210
Feedback Compensation
The RT9210 is a voltage mode controller; the control loop
is a single voltage feedback path including an error amplifier
and PWM comparator as Figure 1 shows. In order to
achieve fast transient response and accurate output
regulation, a adequate compensator design is necessary.
The goal of the compensation network is to provide
adequate phase margin (greater than 45 degrees) and the
highest 0dB crossing frequency. And to manipulate loop
frequency response that its gain crosses over 0dB at a
slope of -20dB/dec.
Modulator Frequency Equations
The modulator transfer function is the small-signal transfer
function of V
by a DC gain and the output filter (L
double pole
frequency at F
modulator is the input voltage (V
to-peak oscillator voltage V
The first step is to calculate the complex conjugate poles
contributed by the LC output filter.
www.richtek.com
14
Comparator
PWM
OUT
VRAMP
LC
/V
and a zero at F
E/A
PWM
+
-
. This transfer function is dominated
Figure 1
RAMP
Vin
Zf
.
Compensator
ESR
IN
+
-
) divided by the peak-
. The DC gain of the
Lo
O
VREF
Zc
and C
ESR
Co
Vout
O
), with a
Preliminary
The output LC filter introduces a double pole,
decade gain slope above its corner resonant frequency,
and a total phase lag of 180 degrees. The Resonant
frequency of the LC filter expressed as follows :
The next step of compensation design is to calculate the
ESR zero. The ESR zero is contributed by the ESR
associated with the output capacitance. Note that this
requires that the output capacitor should have enough ESR
to satisfy stability requirements. The ESR zero of the
output capacitor expressed as follows :
Compensation Frequency Equations
The compensation network consists of the error amplifier
and the impedance networks Z
Figure 3 shows the DC-DC converter's gain vs. frequency.
The compensation gain uses external impedance networks
Z
F
F
F
C
P1
Z1
P1
and Z
=
=
=
0
2
2
π
π
F
×
×
to provide a stable, high bandwidth loop.
R
R
1
2
2
COMP1
RT9210
×
1
(C
C
F
1
F
2
//
Z(ESR)
R2
P(LC)
EA
C
+
Zf
-
2
C1
)
VREF
=
C2
=
Figure 2
2
2
π
π
FB1
×
×
C
C
and Z
L
1
O
1
Rf
DS9210-05 March 2007
O
×
×
ESR
Zc
C
R1
F
O
as Figure 2 shows.
V
OUT
−
40dB/