ingr165b ETC-unknow, ingr165b Datasheet - Page 5

• Manufacturer Part Number: ingr165b
• Description: 1.32 Gbit/s Serial Link Transmitter And Receiver
• Manufacturer: ETC-unknow

2.2.3 Data Burst Transfers
The data burst timing provides the full data rate of 148.5 MByte/s. VALID is asserted when the first data is
valid at PDATA[35.0]. With every rising edge of RDCLK the PDATA inputs are registered, serialized and
transmitted. VALID can remain asserted as long as new data are available.
In the timing diagram PARGEN is de-asserted and the application delivers the PARITY bit synchronously
to the data word.
Note : For timings with assertion of FLAGI, please see section 3.2.5
10/2003 - rev. 2.0
Parameter
t
t
t
t
t
t
t
VALID
RDCLK
PDATA [35..0]
PARITY
1
2
2-1
2-2
3
4
5
LOCK#
RESET#
Table 1: INGT165B Data Burst Timing Parameters (under recommended operating conditions)
*A dislock pulse generates an internal transmitter reset. Therefore both signals have to be at least
50us at high state before transmitter is operational.
Description
Setup time PDATA and PARITY to RDCLK rising edge
VALID active to first rising RDCLK edge
VALID high state
LOCK# / RESET# high state before Tx operational *
PDATA and PARITY hold time
RDCLK cycle time (without assertion of FLAGI)
Rising RDCLK edge to sampling window for VALID state
(VALID=0: exit BURST mode,
VALID=1: continue BURST mode)
Figure 4: INGT165B Data Burst Timing Diagram
t
2-2
PARITY1
t
1
DW1
t
2-1
t
2
t
3
PARITY2
DW2
INGT165B / INGR165B
t
5
Min.
t
50
9
9
5
9
18
4
PARITY3
DW3
30.3
Typ.
12
20
6
4
6
t
Max.
5
14
22
Unit
ns
ns
ns
µs
ns
ns
ns
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