isplsi2032e-225lt48 Lattice Semiconductor Corp., isplsi2032e-225lt48 Datasheet
isplsi2032e-225lt48
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isplsi2032e-225lt48 Summary of contents
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... Optimized Global Routing Pool Provides Global Interconnectivity Copyright © 2003 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. ...
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Functional Block Diagram Figure 1. ispLSI 2032E Functional Block Diagram GOE 0 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 ...
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Absolute Maximum Ratings Supply Voltage V .................................. -0.5 to +7.0V cc Input Voltage Applied ........................ -2 Off-State Output Voltage Applied ..... -2 Storage Temperature ................................ -65 to 150°C Case Temp. with Power Applied .............. -55 to ...
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Switching Test Conditions Input Pulse Levels Input Rise and Fall Time 10% to 90% Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. Output Load Conditions (see Figure 2) TEST ...
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External Timing Parameters TEST 2 PARAMETER # 4 COND Data Prop. Delay, 4PT Bypass, ORP Bypass pd1 Data Prop. Delay pd2 f max A 3 Clk Frequency with Int. Feedback f – 4 Clk ...
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External Timing Parameters TEST 2 PARAMETER # 4 COND Data Propagation Delay, 4PT Bypass, ORP Bypass pd1 Data Propagation Delay pd2 Clock Frequency with Internal Feedback max f – 4 Clock ...
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Internal Timing Parameters 2 PARAMETER # Inputs Input Buffer Delay t 21 Dedicated Input Delay din GRP t grp 22 GRP Delay GLB Product Term Bypass Path Delay (Combinatorial) 4ptbpc Product ...
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Internal Timing Parameters 2 PARAMETER # Inputs t 20 Input Buffer Delay Dedicated Input Delay din GRP t 22 GRP Delay grp GLB Product Term Bypass Path Delay (Combinatorial) 4ptbpc Product ...
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Timing Model I/O Cell Ded. In #21 I/O Delay I/O Pin #20 (Input) #45 Reset #43, 44 Y0,1,2 GOE Derivations of su, h and co from the Product Term Clock Logic ...
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Power Consumption Power consumption in the ispLSI 2032E device depends on two primary factors: the speed at which the device is operating and the number of Product Terms used. Figure 3. Typical Device Power Consumption vs fmax 150 140 130 ...
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Pin Description 44-PIN PLCC PIN NUMBERS NAME I I/O 3 15, 16, 17, 18, I I/O 7 19, 20, 21, 22, I I/O 11 25, 26, 27, 28, I I/O 15 29, ...
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Pin Configuration ispLSI 2032E 44-Pin PLCC Pinout Diagram I/O 28 I/O 29 I VCC BSCAN 1 TDI/IN 0 I/O 0 I Pins have dual function capability pins are not to ...
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Pin Configuration ispLSI 2032E 48-Pin TQFP Pinout Diagram I/O 28 I/O 29 I VCC BSCAN 1 TDI/IN 0 I/O 0 I/O 1 I/O 2 GND 1. Pins have dual function capability pins are not ...
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Part Number Description ispLSI 2032E Device Family Device Number Speed f 225 = 225 MHz max f 200 = 200 MHz max f 180 = 180 MHz max f 135 = 135 MHz max f 110 = 110 MHz max ...