as7c33128ft3236b ETC-unknow, as7c33128ft3236b Datasheet
as7c33128ft3236b
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as7c33128ft3236b Summary of contents
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February 2005 3.3V 128K × 32/36 Flow Through Synchronous SRAM Features • Organization: 131,072 words × bits • Fast clock to data access: 6.5/7.5/8.0/10.0 ns • Fast OE access time: 3.5/4.0 ns • Fully synchronous flow through ...
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Mb Synchronous SRAM products list Org Part Number 256KX18 AS7C33256PFS18B 128KX32 AS7C33128PFS32B 128KX36 AS7C33128PFS36B 256KX18 AS7C33256PFD18B 128KX32 AS7C33128PFD32B 128KX36 AS7C33128PFD36B 256KX18 AS7C33256FT18B 128KX32 AS7C33128FT32B 128KX36 AS7C33128FT36B 256KX18 AS7C33256NTD18B 128KX32 AS7C33128NTD32B 128KX36 AS7C33128NTD36B 256KX18 AS7C33256NTF18B 128KX32 AS7C33128NTF32B 128KX36 AS7C33128NTF36B 1 ...
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Pin arrangement DQP / DDQ V 5 SSQ SSQ V 11 DDQ ...
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Functional description The AS7C33128FT32B/36B is a high-performance CMOS 4-Mbit synchronous Static Random Access Memory (SRAM) device organized as 131,072 words × bits. Fast cycle times of 7.5/8.5/10/12 ns with clock access times (t expansion. Burst operation is ...
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Signal descriptions Pin I/O Properties CLK I CLOCK Clock. All inputs except OE, ZZ, and LBO are synchronous to this clock. A,A0,A1 I SYNC Address. Sampled when all chip enables are active and when ADSC or ADSP are asserted. DQ[a,b,c,d] ...
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Write enable truth table (per byte) Function GWE BWE L Write All Bytes H H Write Byte a H Write Byte c and d H Read H Key don’t care low high ...
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Synchronous truth table 1 CE0 CE1 CE2 ADSP ADSC ...
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Absolute maximum ratings Parameter Power supply voltage relative to GND Input voltage relative to GND (input pins) Input voltage relative to GND (I/O pins) Power dissipation DC output current Storage temperature (plastic) Temperature under bias Note: Stresses greater than those ...
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DC electrical characteristics for 3.3V I/O operation Parameter Sym † Input leakage current |I LI Output leakage current |I LO Input high (logic 1) voltage V Input low (logic 0) voltage V Output high voltage V OH Output low voltage ...
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Timing characteristics over operating range Parameter Cycle time Clock access time Output enable LOW to data valid Clock HIGH to output Low Z Data output invalid from clock HIGH Output enable LOW to output Low Z Output enable HIGH to ...
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Key to switching waveforms Rising input Timing waveform of read cycle CLK t t ADSPS ADSPH ADSP t ADSCS ADSC Address GWE, BWE t t CSS CSH CE0, CE2 CE1 ...
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Timing waveform of write cycle t CH CLK t ADSPS t ADSPH ADSP ADSC Address BWE BW[a:d] t CSS t CSH CE0, CE2 CE1 ADV OE Din D(A1) Read Suspend Q(A1) Note: Ý = XOR ...
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Timing waveform of read/write cycle (ADSP Controlled; ADSC High) CLK t ADSPS t ADSPH ADSP A1 Address BWE BW[a:d] CE0, CE2 CE1 ADV OE Din LZC Dout Q(A1) Read Q(A1) Note: Ý = XOR when LBO = ...
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Timing waveform of read/write cycle(ADSC controlled, ADSP = HIGH) CLK t t ADSCS ADSCH ADSC ADDRESS BWE BW[a: CSS CSH CE0,CE2 CE1 LZOE Q(A1) Q(A2) Dout Din READ READ READ Q(A1) ...
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Timing waveform of power down cycle CLK t t ADSPS ADSPS ADSP ADSC A1 ADDRESS BWE BW[a: CSS CSH CE0,CE2 CE1 ADV LZOE Din t HZC Dout Q(A1) t PDS ZZ ZZ Setup Cycle ...
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AC test conditions • Output load: see Figure B, except for t • Input pulse level: GND to 3V. See Figure A. • Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A. • Input ...
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Package Dimensions 100-pin quad flat pack (TQFP TQFP Min Max A1 0.05 0.15 A2 1.35 1.45 b 0.22 0.38 c 0.09 0.20 D 13.90 14.10 E 19.90 20.10 e 0.65 nominal Hd 15.85 16.15 He 21.80 22.20 ...
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Ordering information Package Width –65 AS7C33128FT32B- TQFP x32 65TQC AS7C33128FT32B- TQFP x32 65TQI AS7C33128FT36B- TQFP x36 65TQC AS7C33128FT36B- TQFP x36 65TQI Note: Add suffix ‘N’ to the above part numbers for Lead Free Parts (Ex. Part numbering guide AS7C 33 ...
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