as7c33128ft18b ETC-unknow, as7c33128ft18b Datasheet - Page 4

• Manufacturer Part Number: as7c33128ft18b
• Manufacturer: ETC-unknow

Functional description
The AS7C33128FT18B is a high-performance CMOS 2-Mbit synchronous Static Random Access Memory (SRAM) device organized as
131,072 words × 18 bits.
Fast cycle times of 7.5/8.5/10/12 ns with clock access times (t
expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC), or the processor address strobe (ADSP).
The burst advance pin (ADV) allows subsequent internally generated burst addresses.
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address
register when ADSP is sampled low, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation, the
data accessed by the current address registered in the address registers by the positive edge of CLK are carried to the data-out buffer. ADV
is ignored on the clock edge that samples ADSP asserted, but is sampled on all subsequent clock edges. Address is incremented internally
for the next access of the burst when ADV is sampled low and both address strobes are high. Burst mode is selectable with the LBO input.
With LBO unconnected or driven high, burst operations use an interleaved count sequence. With LBO driven low, the device uses a linear
count sequence.
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all
18 bits regardless of the state of individual BW[a,b] inputs. Alternately, when GWE is high, one or more bytes may be written by asserting
BWE and the appropriate individual byte BWn signals.
BWn is ignored on the clock edge that samples ADSP low, but it is sampled on all subsequent clock edges. Output buffers are disabled
when BWn is sampled LOW regardless of OE. Data is clocked into the data input register when BWn is sampled low. Address is
incremented internally to the next burst address if BWn and ADV are sampled low.
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP
are as follows:
The AS7C33128FT18B family operates from a core 3.3V power supply. I/Os use a separate power supply that can operate at 2.5V or 3.3V.
These devices are available in a 100-pin TQFP package.
TQFP capacitance
*Guaranteed not tested
TQFP thermal resistance
1 This parameter is sampled
12/10/04; v.1.3
Input capacitance
I/O capacitance
Thermal resistance
(junction to ambient)
Thermal resistance
(junction to top of case)
• ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.
• WE signals are sampled on the clock edge that samples ADSC low (and ADSP high).
• Master chip enable CE0 blocks ADSP, but not ADSC.
Description
Parameter
1
1
Test conditions follow standard test methods and
procedures for measuring thermal impedance,
Symbol
C
C
I/O
IN
*
*
Alliance Semiconductor
per EIA/JESD51
Conditions
CD
Test conditions
) of 6.5/7.5/8.0/10 ns. Three chip enable (CE) inputs permit easy memory
V
V
OUT
IN
= 0V
= 0V
®
1–layer
4–layer
Min
Symbol
-
-
θ
θ
θ
JA
JA
JC
AS7C33128FT18B
Typical
Max
40
22
8
5
7
P. 4 of 19
Units
°C/W
°C/W
°C/W
Unit
pF
pF