as7c33256pfd3236a ETC-unknow, as7c33256pfd3236a Datasheet

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as7c33256pfd3236a

Manufacturer Part Number
as7c33256pfd3236a
Description
Manufacturer
ETC-unknow
Datasheet
December 2004
Selection guide
Features
• Organization: 262,144 words x 32 or 36 bits
• Fast clock speeds to 166 MHz
• Fast clock to data access: 3.5/4.0 ns
• Fast OE access time: 3.5/4.0 ns
• Fully synchronous register-to-register operation
• Dual-cycle deselect
• Asynchronous output enable control
• Available in100-pin TQFP
Logic block diagram
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
12/1/04, v.1.2
3.3V 256K × 32/36 pipelined burst synchronous SRAM
A[17:0]
ADSC
ADSP
BWE
CLK
ADV
GWE
BW
BW
BW
BW
CE0
CE1
CE2
OE
ZZ
a
d
c
b
Alliance Semiconductor
Power
down
18
D
D
CE
CLK
CLK
D
CLK
D
CLK
D
CLK
D
CE
CLK
D
CLK
CLK
CE
CLR
Byte write
Byte write
Byte write
Byte write
registers
registers
registers
registers
register
Enable
Address
register
delay
register
DQ
DQ
DQ
DQ
Enable
d
c
b
a
Q
Burst logic
Q
Q
Q
Q
Q
Q
• Individual byte write and global write
• Multiple chip enables for easy expansion
• Linear or interleaved burst control
• Snooze mode for reduced power-standby
• Common data inputs and data outputs
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate V
LBO
–166
166
475
130
18
3.5
30
Q0
Q1
6
2
®
16
2
18
CLK
OE
registers
36/32
Output
4
256K × 32/36
Memory
36/32
array
DQ[a:d]
36/32
CLK
registers
Input
AS7C33256PFD32A
AS7C33256PFD36A
Copyright ©Alliance Semiconductor. All rights reserved.
–133
133
425
100
7.5
30
4
P. 1 of 20
DDQ
Units
MHz
mA
mA
mA
ns
ns

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as7c33256pfd3236a Summary of contents

Page 1

December 2004 3.3V 256K × 32/36 pipelined burst synchronous SRAM Features • Organization: 262,144 words bits • Fast clock speeds to 166 MHz • Fast clock to data access: 3.5/4.0 ns • Fast OE access time: ...

Page 2

Mb Synchronous SRAM products list Org Part Number 512KX18 AS7C33512PFS18A 256KX32 AS7C33256PFS32A 256KX36 AS7C33256PFS36A 512KX18 AS7C33512PFD18A 256KX32 AS7C33256PFD32A 256KX36 AS7C33256PFD36A 512KX18 AS7C33512FT18A 256KX32 AS7C33256FT32A 256KX36 AS7C33256FT36A 512KX18 AS7C33512NTD18A 256KX32 AS7C33256NTD32A 256KX36 AS7C33256NTD36A 512KX18 AS7C33512NTF18A 256KX32 AS7C33256NTF32A 256KX36 AS7C33256NTF36A 1 ...

Page 3

Pin arrangement TQFP DQP / DDQ V 5 SSQ SSQ V 11 DDQ ...

Page 4

Functional description The AS7C33256PFD32A and AS7C33256PFD36A are high-performance CMOS 8-Mbit Synchronous Static Random Access Memory (SRAM) devices organized as 262,144 words bits, and incorporate a two-stage register-register pipeline for highest frequency on any given technology. Fast ...

Page 5

Signal descriptions Signal I/O Properties Description CLK I CLOCK Clock. All inputs except OE, ZZ, LBO are synchronous to this clock SYNC Address. Sampled when all chip enables are active and ADSC or ADSP are asserted. ...

Page 6

Write enable truth table (per byte) Function GWE BWE L Write All Bytes H Write Byte a H Write Byte c and Read H Key don’t care low high ...

Page 7

Synchronous truth table 1 CE0 CE1 CE2 ADSP ADSC ...

Page 8

Absolute maximum ratings Parameter Power supply voltage relative to GND Input voltage relative to GND (input pins) Input voltage relative to GND (I/O pins) Power dissipation Short circuit output current Storage temperature (plastic) Temperature under bias Recommended operating conditions ...

Page 9

DC electrical characteristics for 3.3V I/O operation Parameter 1 Input leakage current Output leakage current Input high (logic 1) voltage Input low (logic 0) voltage Output high voltage Output low voltage 1 LBO, and ZZ pins have an internal pull-up ...

Page 10

Timing characteristics for 3.3 V I/O operation Parameter Clock frequency Cycle time Clock access time Output enable low to data valid Clock high to output low Z Data output invalid from clock high Output enable low to output low Z ...

Page 11

Timing characteristics for 2.5 V I/O operation Parameter Clock frequency Cycle time Clock access time Output enable low to data valid Clock high to output low Z Data output invalid from clock high Output enable low to output low Z ...

Page 12

Key to switching waveforms Rising input Timing waveform of read cycle CLK t ADSPS t ADSPH ADSP t ADSCS ADSC Address GWE, BWE t t CSS CSH CE0, CE2 CE1 ...

Page 13

Timing waveform of write cycle t CH CLK t t ADSPS ADSPH ADSP ADSC Address BWE BW[a: CSS CSH CE0, CE2 CE1 ADV OE Din D(A1) Read Sus- Q(A1) pend Write D(A1) Note: ...

Page 14

Timing waveform of read/write cycle (ADSP Controlled; ADSC High) CLK t t ADSPH ADSPS ADSP Address A1 GWE CE0, CE2 CE1 ADV OE Din Dout DSEL Read Q(A1) Note: Ý = XOR when LBO = high/no connect; Ý = ADD ...

Page 15

Timing waveform of read/write cycle(ADSC controlled, ADSP = HIGH) CLK t t ADSCS ADSCH ADSC ADDRESS GWE t t CSS CSH CE0,CE2 CE1 ADV LZOE Q(A1) Dout Din READ READ READ Q(A1) Q(A2) ...

Page 16

Timing waveform of power down cycle CLK t t ADSPS ADSPS ADSP ADSC A1 ADDRESS GWE t t CSS CSH CE0,CE2 CE1 ADV LZOE Din Dout Q(A1 Setup Cycle I supply S READ USPEND ...

Page 17

AC test conditions • Output load: see Figure B, except for t • Input pulse level: GND to 3V. See Figure A. • Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A. • Input ...

Page 18

Package dimensions: 100-pin quad flat pack (TQFP) TQFP Min Max A1 0.05 0.15 A2 1.35 1.45 b 0.22 0.38 c 0.09 0.20 D 13.80 14.20 E 19.80 20.20 e 0.65 nominal Hd 15.80 16.20 He 21.80 22.20 L 0.45 0.75 ...

Page 19

Ordering information Package TQFP x 32 TQFP x 36 Note: Add suffix ‘N’ with the above part number for Lead Free Parts (Ex. AS7C33256PFD32A-166TQCN) Part numbering guide AS7C 33 256 Alliance Semiconductor SRAM prefix ...

Page 20

Alliance Semiconductor Corporation ® 2575, Augustine Drive, Santa Clara, CA 95054 Tel: 408 - 855 - 4900 Fax: 408 - 855 - 4999 www.alsc.com © Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt ...

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