as7c251mntd18a ETC-unknow, as7c251mntd18a Datasheet
as7c251mntd18a
Related parts for as7c251mntd18a
as7c251mntd18a Summary of contents
Page 1
... CLK D Write delay addr. registers CLK Control logic CLK 18 18 Data D Q input register CLK OE -166 6 166 3.5 290 85 40 Alliance Semiconductor AS7C251MNTD18A CLK SRAM array CLK Output register [a,b] -133 Units 7.5 ns 133 MHz 3.8 ns 270 mA 75 ...
Page 2
... Mode PL-SCD PL-SCD PL-SCD PL-DCD PL-DCD PL-DCD NTD-PL NTD-PL NTD-PL NTD-FT NTD-FT NTD- Alliance Semiconductor AS7C251MNTD18A Speed 166/133 MHz 166/133 MHz 166/133 MHz 166/133 MHz 166/133 MHz 166/133 MHz 7.5/8.5/10 ns 7.5/8.5/10 ns 7.5/8.5/10 ns 166/133 MHz 166/133 MHz 166/133 MHz 7.5/8.5/10 ns 7.5/8.5/10 ns 7.5/8.5/ ...
Page 3
... V 20 DDQ V 21 SSQ DQb6 22 DQb7 23 24 DQPb SSQ V 27 DDQ 12/23/04, v.2.2 ® TQFP 14 x 20mm Alliance Semiconductor AS7C251MNTD18A DDQ 76 V SSQ 75 NC DQPa 74 DQa7 73 72 DQa6 V 71 SSQ 70 V DDQ 69 DQa5 68 DQa4 ...
Page 4
... Functional description The AS7C251MNTD18A family is a high performance CMOS 16-Mbit synchronous Static Random Access Memory (SRAM) organized as 1,048,576 words × 18 bits and incorporates a LATE LATE Write. This variation of the 16Mb+ synchronous SRAM uses the No Turnaround Delay (NTD operation that improves bandwidth over pipelined burst devices normal pipelined burst device, the write data, command, and address are all applied to the device on the same clock edge ...
Page 5
... DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE PUS MODE. 12/23/04, v.2.2 ® or left floating, device follows interleaved Burst order. When DD is guaranteed after the time t is met. After entering SNOOZE MODE, all inputs except ZZ SB2 ZZI Alliance Semiconductor AS7C251MNTD18A . The duration of SB2 ...
Page 6
... L External NOP/WRITE ABORT (Begin Burst) High Next Current enables WRITEs to byte “b” (DQb pins); Alliance Semiconductor AS7C251MNTD18A Linear burst order (LBO = 0) A1A0 A1A0 A1A0 ...
Page 7
... DDQ OUT T stg T bias Symbol Min Nominal V 2.375 2 2.375 2.5 DDQ Vss 0 0 Alliance Semiconductor AS7C251MNTD18A Burst Dsel Burst Burst Min Max Unit –0.3 +3.6 –0 0.3 DD –0 0.3 DDQ – 1.8 W – –65 +150 o –65 +150 Max Unit 2 ...
Page 8
... All V – 0.2V, Deselected < Max IL Deselected < 0.2V, ≤ 0.2V or ≥ V all V – 0. ≥ V Deselected Max DD ≤ ≥ V all Alliance Semiconductor AS7C251MNTD18A Min Max < < OUT DDQ 1. 1.7* V DDQ -0.3** 0.7 -0.3** 0.7 1.7 – – 0.7 ...
Page 9
... CENS t 0.5 – CENH t 1.5 – ADVS t 0.5 – ADVH Conditions Symbol ZZ > SB2 t PDS t PUS t ZZI t RZZI Alliance Semiconductor AS7C251MNTD18A -133 1 Min Max Unit Notes – 133 MHz 7.5 – ns – 3.8 ns – 3 – 1.5 – – – ...
Page 10
... Falling input HZOE OE Q(A1) Q(A2) Q(A2Y‘01) Read Continue Continue Continue Q(A2) Read Read Q(A2Y‘10) Q(A2Y‘01) Q(A2Y‘11) Alliance Semiconductor AS7C251MNTD18A Undefined t CYC A3 Q(A2Y‘10) Q(A3) Q(A2Y‘11) Continue Inhibit Read Read Read Clock Q(A3) Q(A3Y‘01 HLZC ...
Page 11
... HZOE Dout Q(n-2) Q(n-1) Write DSEL D(A1) 12/23/04, v.2.2 ® D(A1) D(A2) D(A2Y‘01) Write Continue Continue Continue D(A2) Write Write Write D(A2Y‘10) D(A2Y‘01) D(A2Y‘11) Alliance Semiconductor AS7C251MNTD18A t CYC D(A3) D(A2Y‘10) D(A2Y‘11) Continue Inhibit Write Write Clock D(A3) D(A3Y‘01 ...
Page 12
... Note: Ý = XOR when LBO = high/no connect. Ý = ADD when LBO = low. BW[a:d] is don’t care. 12/23/04, v.2.2 ® LZC OH D(A1) D(A2) Q(A3) D(A2Ý01) Burst Burst Read Read Write Read Q(A3) Q(A4) D(A2Ý01) Q(A4Ý01) Alliance Semiconductor AS7C251MNTD18A t CYC HZC D(A5) Q(A6) Q(A4) Q(A4Ý01) t HZOE t LZOE Write Read Write D(A5) Q(A6) D(A7 DSEL ...
Page 13
... Address A1 D/Q Command Read Burst Q(A1) Q(A1Ý01) Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low low. 12/23/04, v.2.2 ® A2 Q(A1Ý01) Q(A1) Q(A1Ý10) STALL Burst DSEL Burst Q(A1Ý10) DSEL Alliance Semiconductor AS7C251MNTD18A A3 D(A2) Burst Write Write Burst NOP NOP D(A2) D(A2Ý10) D(A2Ý01) D(A3 ...
Page 14
... Timing waveform of snooze mode CLK ZZ setup cycle ZZ t ZZI I supply I SB2 All inputs Deselect or Read Only (except ZZ) Dout 12/23/04, v.2.2 ® t PUS ZZ recovery cycle t RZZI Deselect or Read Only High-Z Alliance Semiconductor AS7C251MNTD18A Normal operation Cycle ...
Page 15
... DDQ 30 pF* Figure B: Output load (A) at any given temperature and voltage. LZC IL Alliance Semiconductor AS7C251MNTD18A Thevenin equivalent: +2.5V 319Ω/1667Ω D OUT /2 5 pF* 353Ω/1538Ω GND *including scope and jig capacitance Figure C: Output load(B) ...
Page 16
... Package dimensions 100-pin quad flat pack (TQFP) TQFP Min Max A1 0.05 0.15 A2 1.35 1.45 b 0.22 0.38 c 0.09 0.20 D 13.90 14.10 E 19.90 20.10 e 0.65 nominal Hd 15.85 16.15 He 21.80 22.20 L 0.45 0.75 L1 1.00 nominal α 0° 7° Dimensions in millimeters 12/23/04, v.2.2 ® Alliance Semiconductor AS7C251MNTD18A b e α ...
Page 17
... Ordering information Width Package & TQFP x18 Note: Add suffix ‘N’ to the above part number for Lead Free Parts (Ex. AS7C251MNTD18A-166TQCN) Part numbering guide AS7C Alliance Semiconductor SRAM prefix 2. Operating voltage 2.5V 3. Organization NTD ™ Turn-Around Delay. Pipelined mode 5 ...
Page 18
... Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. AS7C251MNTD18A ® Copyright © Alliance Semiconductor All Rights Reserved Part Number: AS7C251MNTD18A Document Version: v.2.2 ...