as7c251mpfd3236a ETC-unknow, as7c251mpfd3236a Datasheet

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as7c251mpfd3236a

Manufacturer Part Number
as7c251mpfd3236a
Description
Manufacturer
ETC-unknow
Datasheet
February 2005
Features
• Organization: 1,048,576 words × 32 or 36 bits
• Fast clock speeds to 200 MHz
• Fast clock to data access: 3.1/3.5/3.8 ns
• Fast OE access time: 3.1/3.5/3.8 ns
• Fully synchronous register-to-register operation
• Double-cycle deselect
• Asynchronous output enable control
• Available in 100-pin TQFP package
Logic block diagram
Selection guide
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
2/11/05, v.1.1
A[19:0]
ADSC
ADSP
GWE
BWE
CLK
ADV
BW
BW
BW
BW
CE0
CE1
CE2
2.5V 1M × 32/36 pipelined burst synchronous SRAM
OE
ZZ
a
d
c
b
Power
down
Alliance Semiconductor
20
D
D
CE
CLK
CLK
D
CLK
D
CLK
D
CLK
D
CE
CLK
D
CLK
CLK
CE
CLR
Byte write
Byte write
Byte write
Byte write
registers
registers
registers
registers
register
Enable
Address
register
register
delay
Enable
DQ
DQ
DQ
DQ
b
d
c
a
Burst logic
Q
Q
Q
Q
Q
Q
Q
-200
• Individual byte write and global write
• Multiple chip enables for easy expansion
• 2.5V core power supply
• Linear or interleaved burst control
• Snooze mode for reduced power-standby
• Common data inputs and data outputs
200
450
170
LBO
3.1
90
5
Q0
Q1
20
®
2
18
20
2
CLK
OE
32/36
registers
Output
4
-166
1M × 32/36
166
400
150
3.5
90
Memory
6
DQ[a:d]
32/36
array
32/36
CLK
registers
Input
Copyright © Alliance Semiconductor. All rights reserved.
AS7C251MPFD32A
AS7C251MPFD36A
-133
133
350
140
7.5
3.8
90
1 of 19
Units
MHz
mA
mA
mA
ns
ns

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as7c251mpfd3236a Summary of contents

Page 1

February 2005 2.5V 1M × 32/36 pipelined burst synchronous SRAM Features • Organization: 1,048,576 words × bits • Fast clock speeds to 200 MHz • Fast clock to data access: 3.1/3.5/3.8 ns • Fast OE access time: ...

Page 2

Mb Synchronous SRAM products list Org Part Number 2MX18 AS7C252MPFS18A 1MX32 AS7C251MPFS32A 1MX36 AS7C251MPFS36A 2MX18 AS7C252MPFD18A 1MX32 AS7C251MPFD32A 1MX36 AS7C251MPFD36A 2MX18 AS7C252MFT18A 1MX32 AS7C251MFT32A 1MX36 AS7C251MFT36A 2MX18 AS7C252MNTD18A 1MX32 AS7C251MNTD32A 1MX36 AS7C251MNTD36A 2MX18 AS7C252MNTF18A 1MX32 AS7C251MNTF32A 1MX36 AS7C251MNTF36A ...

Page 3

Pin assignment 100-pin TQFP - top view NC/DQPc 1 DQc0 2 DQc1 DDQ V 5 SSQ 6 DQc2 DQc3 7 8 DQc4 DQc5 SSQ V 11 DDQ 12 DQc6 DQc7 ...

Page 4

Functional description The AS7C251MPFD32A/36A is a high-performance CMOS 32-Mbit synchronous Static Random Access Memory (SRAM) device organized as 1,048,576 words x 32/36. It incorporates a two-stage register-register pipeline for highest frequency on any given technology. Fast cycle times of 5/6/7.5 ...

Page 5

Signal descriptions Pin I/O Properties CLK I CLOCK Clock. All inputs except OE, ZZ, and LBO are synchronous to this clock. A,A0,A1 I SYNC Address. Sampled when all chip enables are active and when ADSC or ADSP are asserted. DQ[a,b,c,d] ...

Page 6

Write enable truth table (per byte) Function GWE BWE L Write All Bytes H Write Byte a H Write Byte c and Read H Key don’t care low high ...

Page 7

Synchronous truth table 1 CE0 CE1 CE2 ADSP ADSC ...

Page 8

Absolute maximum ratings Parameter Power supply voltage relative to GND Input voltage relative to GND (input pins) Input voltage relative to GND (I/O pins) Power dissipation Short circuit output current Storage temperature Temperature under bias Stresses greater than those listed ...

Page 9

DC electrical characteristics Parameter † Input leakage current |I LI Output leakage current |I LO Input high (logic 1) voltage V Input low (logic 0) voltage V Output high voltage V Output low voltage V † LBO and ZZ pins ...

Page 10

Timing characteristics over operating range Parameter Clock frequency Cycle time Clock access time Output enable low to data valid Clock high to output low Z Data output invalid from clock high Output enable low to output low Z Output enable ...

Page 11

Key to switching waveforms Rising input Timing waveform of read cycle CLK t ADSPS t ADSPH ADSP t ADSCS ADSC Address GWE, BWE t t CSS CSH CE0, CE2 CE1 ...

Page 12

Timing waveform of write cycle t CH CLK t t ADSPS ADSPH ADSP ADSC Address BWE BW[a: CSS CSH CE0, CE2 CE1 ADV OE Din D(A1) Read Sus- Q(A1) pend Write D(A1) Note: ...

Page 13

Timing waveform of read/write cycle (ADSP Controlled; ADSC High) CLK t t ADSPS ADSPH ADSP Address A1 GWE CE0, CE2 CE1 ADV OE Din Dout DSEL Read Q(A1) Note: Ý = XOR when LBO = high/no connect; Ý = ADD ...

Page 14

Timing waveform of read/write cycle(ADSC controlled, ADSP = HIGH) CLK t t ADSCS ADSCH ADSC ADDRESS GWE t t CSS CSH CE0,CE2 CE1 ADV LZOE Q(A1) Dout Din READ READ Q(A1) Q(A2) 2/11/05, ...

Page 15

Timing waveform of power down cycle CLK t t ADSPS ADSPS ADSP ADSC A1 ADDRESS GWE t t CSS CSH CE0,CE2 CE1 ADV LZOE Din Dout Q(A1 supply S READ USPEND READ Q(A1) Q(A1) ...

Page 16

AC test conditions • Output load: For LZC LZOE HZOE • Input pulse level: GND to 2.5V. See Figure A. • Input rise and fall time (measured at 0.25V and 2.25V): 2 ns. See Figure ...

Page 17

Package dimensions 100-pin quad flat pack (TQFP) TQFP Min Max A1 0.05 0.15 A2 1.35 1.45 b 0.22 0.38 c 0.09 0.20 D 13.90 14.10 E 19.90 20.10 e 0.65 nominal Hd 15.85 16.15 He 21.80 22.20 L 0.45 0.75 ...

Page 18

Ordering information Package & Width 200 MHz AS7C251MPFD32A-200TQC TQFP x32 AS7C251MPFD32A-200TQI AS7C251MPFD36A-200TQC TQFP x36 AS7C251MPFD36A-200TQI Note: Add suffix ‘N’ to the above part numbers for lead free parts (Ex AS7C251MPFD32A-200TQC Part numbering guide AS7C ...

Page 19

Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Tel: 408 - 855 - 4900 Fax: 408 - 855 - 4999 www.alsc.com © Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt ...

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