as7c25512ntd3236a ETC-unknow, as7c25512ntd3236a Datasheet
as7c25512ntd3236a
Manufacturer Part Number
as7c25512ntd3236a
Description
Manufacturer
ETC-unknow
Datasheet
1.AS7C25512NTD3236A.pdf
(18 pages)
Logic block diagram
Selection guide
Features
• Organization: 524,288 words × 32 or 36 bits
• NTD
• Fast clock speeds to 166 MHz
• Fast clock to data access: 3.5/3.8 ns
• Fast OE access time: 3.5/3.8 ns
• Fully synchronous operation
• Asynchronous output enable control
• Available in 100-pin TQFP package
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
December 2004
12/23/04, v 2.2
™
architecture for efficient bus operation
A[18:0]
CE1
CE2
CE0
DQ[a,b,c,d]
ADV / LD
2.5V 512K × 32/36 Pipelined SRAM with NTD
BWb
BWd
BWa
BWc
LBO
R/W
ZZ
CLK
CEN
32/36
19
D
D
Control
Burst logic
Address
Register
register
logic
CLK
Input
Data
CLK
Alliance Semiconductor
CLK
Q
Q
• Individual byte write and global write
• Clock enable for operation hold
• Multiple chip enables for easy expansion
• 2.5V core power supply
• Self-timed write cycles
• Interleaved or linear burst modes
• Snooze mode for standby operation
19
-166
166
290
OE
3.5
85
40
32/36
6
addr. registers
D
CLK
Write delay
®
32/36
Q
OE
CLK
32/36
CLK
Output
Register
32/36
512K x 32/36
DQ[a,b,c,d]
19
-133
133
270
7.5
3.8
40
SRAM
32/36
75
Array
TM
AS7C25512NTD32A
AS7C25512NTD36A
Copyright © Alliance Semiconductor. All rights reserved.
Units
MHz
mA
mA
mA
ns
ns
P. 1 of 18
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