as7c252mntf18a ETC-unknow, as7c252mntf18a Datasheet - Page 6
![no-image](/images/no-image-200.jpg)
as7c252mntf18a
Manufacturer Part Number
as7c252mntf18a
Description
2.5v 2m X 18 Flowthrough Sram With Ntd
Manufacturer
ETC-unknow
Datasheet
1.AS7C252MNTF18A.pdf
(18 pages)
Burst order
Synchronous truth table
Key: X = Don’t Care, H = HIGH, L = LOW.
signals are LOW.
Notes:
1 CONTINUE BURST cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or WRITE) is chosen in the ini-
tial BEGIN BURST cycle. A CONINUE DESELECT cycle can only be entered if a DESELECT CYCLE is executed first.
2 DUMMY READ and WRITE ABORT cycles can be considered NOPs because the device performs no external operation. A WRITE ABORT means a
WRITE command is given, but no operation is performed.
3 OE may be wired LOW to minimize the number of control signal to the SRAM. The device will automatically turn off the output drivers during a WRITE
cycle. OE may be used when the bus turn-on and turn-off times do not meet an application’s requirements.
4 If an INHIBIT CLOCK command occurs during a READ operation, the DQ bus will remain active (Low-Z). If it occurs during a WRITE cycle, the bus will
remain in High-Z. No WRITE operations will be performed during the INHIBIT CLOCK cycle.
5
6 All inputs except
7 Wait states are inserted by setting
8 This device contains circuitry that will ensure that the outputs will be in High-Z during power-up.
9 The device incorporates a 2-bit burst counter. Address wraps to the initial address every fourth BURST CYCLE.
10 The address counter is incremented for all CONTINUE BURST cycles.
11 ZZ pin is always Low.
Second increment
CE0 CE1 CE2 ADV/LD R/W
BW
Third increment
Starting address
First increment
H
X
X
X
X
X
X
X
X
L
L
L
L
1/17/05, v 1.1
a enables WRITEs to byte “a” (DQa pins);
X
X
L
X
H
X
H
X
H
X
H
X
X
Interleaved burst order (LBO = 1)
X
H
X
X
X
X
X
X
X
L
L
L
L
OE
and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
A1A0
0 0
0 1
1 0
1 1
H
H
H
H
H
X
L
L
L
L
L
L
L
[5,6,7,8,9,11]
CEN
A1A0
0 1
0 0
1 1
1 0
X
X
X
X
H
X
H
X
X
X
X
L
L
HIGH.
BWn = H means all byte write signals (BWa, BWb
A1A0
BWn
BW
0 0
1 0
1 1
0 1
X
X
X
X
X
X
X
X
H
H
X
L
L
b enables WRITEs to byte “b” (DQb pins).
A1A0
OE CEN
1 1
1 0
0 1
0 0
X
X
X
X
H
H
X
X
X
X
X
L
L
Alliance Semiconductor
H
L
L
L
L
L
L
L
L
L
L
L
L
Second increment
Starting Address
Third increment
First increment
External L to H NOP/DUMMY READ (Begin Burst) High-Z
External L to H
External L to H
External L to H NOP/WRITE ABORT (Begin Burst) High-Z
Address
Current L to H
source
Next
Next
Next
Next
NA
NA
NA
NA
Linear burst order (LBO = 0)
®
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
CLK
A1A0
0 0
0 1
1 0
1 1
DUMMY READ (Continue Burst)
WRITE CYCLE (Continue Burst)
WRITE ABORT (Continue Burst)
CONTINUE DESELECT Cycle
READ Cycle (Continue Burst)
WRITE CYCLE (Begin Burst)
) are HIGH.
READ Cycle (Begin Burst)
A1A0
0 1
1 0
1 1
0 0
DESELECT Cycle
DESELECT Cycle
DESELECT Cycle
INHIBIT CLOCK
Operation
BW
A1A0
AS7C252MNTF18A
1 0
1 1
0 0
0 1
n = L means one or more byte write
A1A0
1 1
0 0
0 1
1 0
P. 6 of 18
High-Z
High-Z
High-Z
High-Z
High-Z 1,2,10
High-Z
DQ
Q
Q
D
D
-
1,3,10
1,2,3,
Notes
1,10
2,3
10
2
4
1
3