as7c252mft18a ETC-unknow, as7c252mft18a Datasheet - Page 16

• Manufacturer Part Number: as7c252mft18a
• Manufacturer: ETC-unknow

AC test conditions
Notes
1
2
3
4
5
6
8
7
1/17/05, v 1.2
+2.5V
• Output load: For t
• Input pulse level: GND to 2.5V. See Figure A.
• Input rise and fall time (measured at 0.25V and 2.25V): 2 ns. See Figure A.
• Input and output timing reference levels: 1.25V.
For test conditions, see “AC test conditions”, Figures A, B, and C.
This parameter is measured with output load condition in Figure C.
This parameter is sampled but not 100% tested.
t
t
This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must
meet the setup and hold times for all rising edges of CLK when chip is enabled.
Write refers to
Chip select refers to
HZOE
CH
GND
Figure A: Input waveform
is measured as high if above VIH, and t
10%
is less than t
90%
GWE, BWE, and BW[a,b].
LZOE
CE0, CE1, and CE2.
LZC
, and t
, t
90%
LZOE
HZC
10%
is less than t
, t
HZOE
D
OUT
, t
CL
HZC
is measured as low if below VIL.
LZC
Figure B: Output load (A)
, see Figure C. For all others, see Figure B.
at any given temperature and voltage.
Alliance Semiconductor
Z
0
= 50Ω
50Ω
30 pF*
V
®
L
= V
DDQ
/2
353Ω/1538Ω
D
OUT
Figure C: Output load(B)
Thevenin equivalent:
AS7C252MFT18A
319Ω/1667Ω
5 pF*
GND
+2.5V
*including scope
and jig capacitance
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