LMH1982SQ National Semiconductor Corporation, LMH1982SQ Datasheet
LMH1982SQ
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LMH1982SQ Summary of contents
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... SDI output jitter specifications. The LMH1982 is offered in a space-saving 32- pin LLP package and provides low total power dissipation of 250 mW (typical). Typical System Block Diagram © 2008 National Semiconductor Corporation Features ■ Two simultaneous LVDS output clocks with selectable frequencies and Hi-Z capability: — ...
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... Functional Block Diagram Ordering Information Package Part Number LMH1982SQE 32-Pin LLP LMH1982SQ LMH1982SQX www.national.com Package Marking Transport Media 250 Units Tape and Reel L1982SQ 1k Units Tape and Reel 4.5k Units Tape and Reel 2 30052403 NSC Drawing SQA32A ...
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Connection Diagram Pin Descriptions Pin No. Pin Name – DAP 1 VC_FREERUN 2, 10, 18, 22, 26, 30 GND 3, 21, 27, 28 HREF_A 5 VREF_A 6 REF_SEL 7 HREF_B 8 VREF_B SDA ...
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General Description .............................................................................................................................. 1 Features .............................................................................................................................................. 1 Applications ......................................................................................................................................... 1 Typical System Block Diagram ............................................................................................................... 1 Functional Block Diagram ...................................................................................................................... 2 Ordering Information ............................................................................................................................. 2 Connection Diagram ............................................................................................................................. 3 Absolute Maximum Ratings .................................................................................................................... 6 Operating Ratings ................................................................................................................................ 6 Electrical Characteristics ...
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PLL 2 and PLL 3 Charge Pump Current Control Register ................................................................ 23 9.10 Reserved Registers ................................................................................................................. 23 10.0 TYPICAL SYSTEM BLOCK DIAGRAMS ....................................................................................... 24 Physical Dimensions ........................................................................................................................... 26 5 www.national.com ...
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Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. ESD Tolerance (Note 2) Human Body Model Machine Model Supply Voltage Supply Voltage Input Voltage ...
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Clock Outputs (Pins 19, 20, 23, 24) Jitter 27 MHz Time Interval Error SD (TIE) Peak-to-Peak Output Jitter (Note 5) 27 MHz TIE Peak-to-Peak Output Jitter(Note 5) 67.5 MHz TIE Peak-to-Peak Output Jitter (Note 5) Jitter 74.176 MHz TIE Peak-to-Peak ...
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Typical Performance Characteristics Note: Test conditions 3.3V 2.5V, analog video reference from Tektronix TG700 AVG7 (SD video module) and AWVG7 (HD video module), DD VDD H sync and V sync inputs from the LMH1981. NTSC TOF ...
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Application Information 1.0 FUNCTIONAL OVERVIEW The LMH1982 is an analog phase locked loop (PLL) clock generator that can output simultaneous SD and HD video clocks synchronized or “genlocked” sync and V sync in- put reference timing. The LMH1982 ...
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EN_TOF_RST = 0 after the output alignment and be- fore the subsequent output frame. 3.0 MODES OF OPERATION The mode of operation describes the operation of the VCXO PLL, which can operate in either Free Run mode or Genlock ...
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A typical VCXO has an input impedance of several tens of kΩ, which will be the dominant leakage path seen by the loop filter. As the leakage current ...
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www.national.com 12 ...
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INPUT REFERENCE The LMH1982 features two reference ports (A and B) with H sync and V sync inputs which are used for phase locking the outputs in Genlock mode. The reference port can be selected by programming RSEL (register ...
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TABLE 6. HD Clock Frequency Selection HD_CLK (MHz) HD_FREQ Register 08h 74.25 00b 74.25/1.001 01b 148.5 10b 148.5/1.001 11b 5.2 Programming The Output Timing Format When the VCXO PLL is stable and locked to the input refer- ence, the output ...
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The line offset value programmed to TOF_OFFSET can delay or advance the output alignment relative to the reference line where the input H and V pulse are within ΔT (see section 4.2 Internal Reference Frame HV Decoder). TOF_OFFSET ...
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REFERENCE AND PLL LOCK STATUS TABLE 8. Summary of Genlock Status Bits and Flag Outputs Mode Control Bits Conditions GNLK Genlock mode, Reference valid, PLLs locking Genlock mode, Reference valid, PLLs locked Genlock mode, Reference lost, Free Run operation ...
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PLL Lock Status Instability It is possible for excessive jitter on the H input to indicate lock instability through the NO_LOCK output, even if VCXO PLL and output clocks are properly phase locked and no system- level errors are ...
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Lock Time Considerations The LMH1982 lock time or settling time is determined by the loop response of the VCXO PLL, which has a much lower loop bandwidth compared to the integrated PLLs used to derive the other output clock ...
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The subsequent read data transfer shown in Figure 8 consists of a start pulse, the slave device address including the read/ write bit (a one, indicating a read) and the ACK bit. The next byte is the data read from ...
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Genlock And Input Reference Control Registers REGISTER 00h Bits 2-0: H Input Error Max Count (H_ERROR) The H_ERROR bits control the reference detector's error threshold, which determines the maximum number of missing H sync pulses before indicating a LOR. ...
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PLL response. Bit 5: Pin 6 Override (PIN6_OVRD) The PIN6_OVRD bit can be programmed to override the de- fault reference selection capability on pin 6 and instead use pin 6 ...
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REGISTER 0Ah Bits 4-0: TOF Reset (TOF_RST) This register contains the 5 MSBs of TOF_RST. See the de- scription for register 09h. Bit 5: Output Alignment Initialization (TOF_INIT) After enabling output alignment mode (EN_TOF_RST = 1), the TOF_INIT bit should ...
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ICP1 = 8: 250 µA nominal (default) ICP1 = 31: 1000 µA nominal ICP1 step: 31.25 µA nominal current step Bits 7-5: Reserved (RSV) 9.9 PLL 2 and PLL 3 Charge Pump Current Control Register REGISTER 14h Bits 3-0: Charge ...
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TYPICAL SYSTEM BLOCK DIAGRAMS FIGURE 9. Analog Reference Genlock for Triple-rate SDI Video FIGURE 10. SDI Reference Genlock for Triple-rate SDI Video www.national.com 24 30052407 30052408 ...
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FIGURE 11. Triple-rate SDI Loop-through FIGURE 12. Combined Genlock or Loop-through for Triple-rate SDI Video 25 30052409 30052410 www.national.com ...
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Physical Dimensions www.national.com inches (millimeters) unless otherwise noted 32-Pin LLP NS Package Number SQA32A 26 ...
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Notes 27 www.national.com ...
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