micrf004 Micrel Semiconductor, micrf004 Datasheet - Page 9

• Manufacturer Part Number: micrf004
• Description: Micrf004/micrf044 Qwikradio? Low-power Vhf Receiver
• Manufacturer: Micrel Semiconductor

I/O Pin Interface Circuitry
Interface circuitry for the various I/O pins of the MICRF004
are diagrammed in Figures 1 through 6. The ESD protection
diodes at all input and output pins are not shown.
ANT Pin
The ANT pin is internally ac-coupled, through a 3pF capaci-
tor, to an RF N-channel MOSFET, as shown in Figure 1.
Impedance from this pin to VSS is high at low frequencies and
decreases as frequency increases. In the VHF frequency
range, the device input can be modeled as a 6.3k in parallel
with 2pF (pin capacitance) shunt to the VSSRF pin.
CTH Pin
Figure 2 illustrates the CTH-pin interface circuit. The CTH pin
is driven from a P-channel MOSFET source-follower with
approximately 10 A of bias. Transmission gates TG1 and
TG2 isolate the 6.9pF capacitor. Internal control signals
PHI1/PHI2 are related in a manner such that the impedance
across the transmission gates looks like a “resistance” of
approximately 100k . The dc potential at the CTH pin is
approximately 1.6V
CAGC Pin
February 9, 2000
MICRF004/RF044
Demodulator
Timout
2.85Vdc
Signal
Compa-
rator
ANT
Figure 3. CAGC Pin
Figure 1. ANT Pin
Figure 2. CTH Pin
VDDBB
VSSBB
1.5µA
15µA
50
Active
PHI2B
Bias
PHI2
VDDBB
VSSBB
3pF
6k
VSSBB
6.9pF
Active
67.5µA
675µA
Load
PHI1B
PHI1
CAGC
CTH
9
Figure 3 illustrates the CAGC pin interface circuit. The AGC
control voltage is developed as an integrated current into a
capacitor C
the decay current is a 1/10th scaling of this, nominally 1.5 A,
making the attack/decay timeconstant ratio a fixed 10:1.
Signal gain of the RF/IF strip inside the IC diminishes as the
voltage at CAGC decreases. Modification of the attack/decay
ratio is possible by adding resistance from the CAGC pin to
either V
Both the push and pull current sources are disabled during
shutdown, which maintains the voltage across C
improves recovery time in duty-cycled applications. To fur-
ther improve duty-cycle recovery, both push and pull currents
are increased by 45 times for approximately 10ms after
release of the SHUT pin. This allows rapid recovery of any
voltage droop on C
DO and WAKEB Pins
The output stage for DO (digital output) and WAKEB (wakeup
output) is shown in Figure 4. The output is a 10 A push and
10 A pull switched-current stage. This output stage is ca-
pable of driving CMOS loads. An external buffer-driver is
recommended for driving high-capacitance loads.
REFOSC Pin
The REFOSC input circuit is shown in Figure 5. Input imped-
ance is high (200k ). This is a Colpitts oscillator with internal
30pF capacitors. This input is intended to work with standard
ceramic resonators connected from this pin to the VSSBB
pin, although a crystal may be used when greater frequency
accuracy is required. The nominal dc bias voltage on this pin
is 1.4V.
DDBB
AGC
Figure 4. DO and WAKEB Pins
or V
. The attack current is nominally 15 A, while
Figure 5. REFOSC Pin
SSBB
REFOSC
AGC
Compa-
rator
, as desired.
30pF
30pF
while in shutdown.
VSSBB
Active
Bias
250
VDDBB
200k
VSSBB
30µA
10µA
10µA
VDDBB
VSSBB
DO
MICRF004/RF044
AGC
Micrel
, and