micrf507ymltr Micrel Semiconductor, micrf507ymltr Datasheet - Page 13
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micrf507ymltr
Manufacturer Part Number
micrf507ymltr
Description
470mhz To 510mhz Low-power Fsk Transceiver With +10dbm Power Amplifier
Manufacturer
Micrel Semiconductor
Datasheet
1.MICRF507YMLTR.pdf
(46 pages)
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Reading
Any number of registers with consecutive addresses, from
one up to all 23, can be read.
Procedure:
March 2010
Micrel, Inc.
•
•
Bring CS active (high). IO is initially an input.
Clock in a byte consisting of the address bits and
the R/W bit. The first seven bits are the address
(starting with MSB) of the register, or the first
register if more than one, to be read. The eighth
bit is the R/W bit, which is 1 as this is a read
operation. After the R/W bit is clocked in (falling
edge of SCLK), the next rising edge on SCLK will
enable IO as an output for the duration of the
transaction.
Figure 4. Definitions of Control Interface Timing Parameters
Figure 3. Reading a Byte from a Register
13
Figure 3 shows how to read one register. To read more
registers at consecutive addresses, continue pulsing SCLK
eight times for each register to be read before de-asserting
CS.
•
•
Clock out 8 bits per register (one or more) to be
read through IO, MSB first. Rising edges of SCLK
bring each bit to IO. The user can then
conveniently sample the bit at the next falling edge
of SCLK.
Bring CS low to end the transaction. IO reverts to
being an input.
M9999-032210-B
MICRF507
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