54act174 National Semiconductor Corporation, 54act174 Datasheet - Page 2
54act174
Manufacturer Part Number
54act174
Description
Hex D Flip-flop With Master Reset
Manufacturer
National Semiconductor Corporation
Datasheet
1.54ACT174.pdf
(8 pages)
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Connection Diagrams
Functional Description
The ’AC/’ACT174 consists of six edge-triggered D flip-flops
with individual D inputs and Q outputs. The Clock (CP) and
Master Reset (MR) are common to all flip-flops. Each D in-
put’s state is transferred to the corresponding flip-flop’s out-
put following the LOW-to-HIGH Clock (CP) transition. A LOW
input to the Master Reset (MR) will force all outputs LOW in-
dependent of Clock or Data inputs. The ’AC/’ACT174 is use-
ful for applications where the true output only is required and
the Clock and Master Reset are common to all storage
elements.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
for DIP and Flatpak
Pin Assignment
DS100277-3
2
Truth Table
H = HIGH Voltage Level
L = LOW Voltage Level
N
X = Immaterial
= LOW-to-HIGH Transition
MR
H
H
H
L
Inputs
CP
N
N
X
L
Pin Assignment
for LCC
D
X
H
X
L
DS100277-4
Output
DS100277-5
Q
Q
H
L
L