ak4640 ETC-unknow, ak4640 Datasheet - Page 42

• Manufacturer Part Number: ak4640
• Description: 16bit Codec With /hp/spk-ampl
• Manufacturer: ETC-unknow

ASAHI KASEI
(2) I
The AK4640 supports the standard-mode I
system (max: 400kHz).
(2)-1. WRITE Operations
Figure 31 shows the data transfer sequence for the I
HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 37). After the
START condition, a slave address is sent. This address is 7 bits long followed by an eighth bit that is a data direction bit
(R/W). The most significant five bits of the slave address are fixed as “00100”. The next two bits are CAD1 and CAD0
(device address bits). These two bits identify the specific device on the bus. The hard-wired input pins (CAD1 and CAD0
pins) set these device address bits (Figure 32). If the slave address matches that of the AK4640, the AK4640 generates an
acknowledge and the operation is executed. The master must generate the acknowledge-related clock pulse and release
the SDA line (HIGH) during the acknowledge clock pulse (Figure 38). A R/W bit value of “1” indicates that the read
operation is to be executed. A “0” indicates that the write operation is to be executed.
The second byte consists of the control register address of the AK4640. The format is MSB first, and those most
significant 3-bits are fixed to zeros (Figure 33). The data after the second byte contains control data. The format is MSB
first, 8bits (Figure 34). The AK4640 generates an acknowledge after each byte has been received. A data transfer is
always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL
is HIGH defines a STOP condition (Figure 37).
The AK4640 can perform more than one byte write operation per sequence. After receipt of the third byte the AK4640
generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the
write cycle after the first data byte is transferred. After receiving each data packet the internal 5-bit address counter is
incremented by one, and the next data is automatically taken into the next address.
The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data
line can only change when the clock signal on the SCL line is LOW (Figure 39) except for the START and STOP
conditions.
MS0273-E-00
2
C-bus Control Mode (I2C pin = “H”)
SDA
S
T
A
R
T
S
Slave
Address
D7
0
0
R/W="0"
Figure 31. Data Transfer Sequence at the I
C
A
K
D6
(Those CAD1/0 should match with CAD1/0 pins)
0
0
Figure 34. Byte Structure after the second byte
Sub
Address(n)
2
C-bus (max: 100kHz). The AK4640 does not support a fast-mode I
D5
1
0
Figure 33. The Second Byte
Figure 32. The First Byte
A
C
K
2
C-bus mode. All commands are preceded by a START condition. A
Data(n)
A4
D4
0
- 42 -
C
A
K
A3
D3
0
Data(n+1)
CAD1
2
A2
D2
C-Bus Mode
A
C
K
CAD0
A1
D1
C
A
K
Data(n+x)
R/W
A0
D0
A
C
K
S
T
O
P
P
[AK4640]
2
C-bus
2004/03