mt88e41as Zarlink Semiconductor, mt88e41as Datasheet - Page 3

• Manufacturer Part Number: mt88e41as
• Description: Cmos Extended Voltage Calling Number Identification Circuit Ecnic
• Manufacturer: Zarlink Semiconductor

Office. The received data can be processed externally by a microcontroller, stored in memory, or displayed as
is, depending on the application.
MT88E41
2
Pin Description Table
16
10
11
12
1
2
3
4
5
6
7
8
9
Pin
20
10
11
12
13
14
#
1
2
3
4
5
7
9
OSC1
OSC2
VRef
CAP
VSS
IN+
GS
IN-
16 PIN PLASTIC DIP/SOIC
Name
OSC1 Oscillator (Input). Crystal connection. This pin can be driven directly from an
OSC2 Oscillator (Output). Crystal connection. When OSC1 is driven by an external
DCLK Data Clock (Output). Outputs a clock burst of 8 low going pulses at 1202.8Hz
DATA Data (Output). Serial data output corresponding to the FSK input and switching at
CAP Capacitor. Connect a 0.1 F capacitor to V
V
IN+
V
IN-
GS
DR
CD
Ref
SS
1
2
3
4
5
6
7
8
Non-inverting Op-Amp (Input).
Inverting Op-Amp (Input).
Gain Select (Output). Gives access to op-amp output for connection of feedback
resistor.
Voltage Reference (Output). Nominally V
inputs.
external clocking source.
clock, this pin should be left open.
Power supply ground.
(3.5795MHz divided by 2976). Every clock burst is initiated by the DATA stop bit
start bit sequence. When the input DATA is 1202.8 baud, the positive edge of each
DCLK pulse coincides with the middle of the data bits output at the DATA pin. No
DCLK pulses are generated during the start or stop bits. Typically, DCLK is used to
clock the eight data bits from the 10 bit data word into a serial-to-parallel converter.
the input baud rate. Mark frequency at the input corresponds to a logic high, while
space frequency corresponds to a logic low at the DATA output. With no FSK
input, DATA is at logic high. This output stays high until CD has become active.
Data Ready (Open Drain Output). This output goes low after the last DCLK pulse
of each word. This can be used to identify the data (8-bit word) boundary on the
serial output stream. Typically, DR is used to latch the eight data bits from the
serial-to-parallel converter into a microcontroller.
Carrier Detect (Open Drain Output). A logic low indicates that a carrier has been
present for a specified time on the line. A time hysteresis is provided to allow for
momentary discontinuity of carrier.
16
15
14
13
12
11
10
9
VDD
IC2
IC1
PWDN
CD
DR
DATA
DCLK
Figure 2 - Pin Connections
Description
OSC1
OSC2
VRef
CAP
VSS
IN+
GS
NC
NC
IN-
DD/2
SS
. This is used to bias the op-amp
.
10
1
2
3
4
5
6
7
8
9
20 PIN SSOP
20
19
18
17
16
15
14
13
12
11
VDD
IC2
NC
NC
PWDN
CD
DR
DATA
DCLK
IC1
Data Sheet
SEMICMF.019