mt8870dsr1-1 Zarlink Semiconductor, mt8870dsr1-1 Datasheet - Page 2

• Manufacturer Part Number: mt8870dsr1-1
• Description: Integrated Dtmf Receiver With Enhance Sensitivity
• Manufacturer: Zarlink Semiconductor

External component count is minimized by on chip provision of a differential input amplifier, clock oscillator and
latched three-state bus interface.
Pin Description
11-
18
10
14
15
16
1
2
3
4
5
6
7
8
9
Pin #
12-
20
10
11
15
17
18
1
2
3
4
5
6
8
9
PWDN
Q1-Q4
Name
OSC1
OSC2
TOE
V
INH
V
IN+
StD
PWDN
ESt
IN-
GS
OSC1
OSC2
Ref
SS
VRef
VSS
INH
IN+
GS
18 PIN PLASTIC DIP/SOIC
IN-
Non-Inverting Op-Amp (Input).
Inverting Op-Amp (Input).
Gain Select. Gives access to output of front end differential amplifier for connection of
feedback resistor.
Reference Voltage (Output). Nominally V
and Fig. 10).
Inhibit (Input). Logic high inhibits the detection of tones representing characters A, B, C
and D. This pin input is internally pulled down.
Power Down (Input). Active high. Powers down the device and inhibits the oscillator. This
pin input is internally pulled down.
Clock (Input).
Clock (Output). A 3.579545 MHz crystal connected between pins OSC1 and OSC2
completes the internal oscillator circuit.
Ground (Input). 0 V typical.
Three State Output Enable (Input). Logic high enables the outputs Q1-Q4. This pin is
pulled up internally.
Three State Data (Output). When enabled by TOE, provide the code corresponding to the
last valid tone-pair received (see Table 1). When TOE is logic low, the data outputs are high
impedance.
Delayed Steering (Output).Presents a logic high when a received tone-pair has been
registered and the output latch updated; returns to logic low when the voltage on St/GT falls
below V
Early Steering (Output). Presents a logic high once the digital algorithm has detected a
valid tone pair (signal condition). Any momentary loss of signal condition will cause ESt to
return to a logic low.
1
2
3
4
5
6
7
8
9
TSt
.
18
17
16
15
14
13
12
11
10
VDD
St/GT
ESt
StD
Q4
Q3
Q2
Q1
TOE
MT8870D/MT8870D-1
Figure 2 - Pin Connections
Zarlink Semiconductor Inc.
2
Description
PWDN
DD
OSC1
OSC2
VRef
VSS
INH
IN+
GS
NC
/2 is used to bias inputs at mid-rail (see Fig. 6
IN-
10
1
2
3
4
5
6
7
8
9
20 PIN SSOP
20
19
18
17
16
15
14
13
12
11
VDD
St/GT
ESt
StD
NC
Q4
Q3
Q2
Q1
TOE
Data Sheet