le57d111 Zarlink Semiconductor, le57d111 Datasheet

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le57d111

Manufacturer Part Number
le57d111
Description
Dual Subscriber Line Interface Circuit
Manufacturer
Zarlink Semiconductor
Datasheet

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APPLICATIONS
FEATURES
A
NOTE: On August 3, 2007, Zarlink Semiconductor acquired the products and
technology of Legerity Holdings.
ORDERING INFORMATION
1.
2.
Le57D111DJC
Le57D111BTC
Ideal for low cost, high performance linecard
applications (CO, DLC)
Meets requirements for countries such as: China,
Korea, Japan, Taiwan, and Australia
Fulfills the following China specifications: GF002-
9002.1
Dual-channel SLIC device with small footprint
On-chip Thermal Management (TMG) feature in Normal
and Reverse Polarity
Control states: Active (Normal and Reverse Polarity),
Standby, and Disconnect
On-hook transmission
Low standby power
–39 to –58 V battery operation
Two-wire impedance set by single external impedance
Device level thermal shutdown
Set on-chip constant-current feed
Programmable ring-trip detect threshold
Only +5 V and battery supply required
The green package meets RoHS Directive 2002/95/EC of the
European Council to minimize the environmental impact of
electrical equipment.
For delivery using a tape and reel packing system, add a "T" suffix
to the OPN (Ordering Part Number) when placing an order.
Device
Voice Solution
32-pin PLCC (Green),
50 dB Reverse Polarity
44-pin eTQFP (Green),
50 dB Reverse Polarity
Package
1
Tube
Tray
Packing
2
Dual Subscriber Line Interface Circuit
DESCRIPTION
The innovative Le5711 dual-channel SLIC device is designed
for high-density POTS applications requiring a small footprint
SLIC device with significant power savings. By combining the
line interface of two channels into one SLIC device, the Le5711
device enables the design of a low cost, high performance, and
fully programmable line interface for multiple country
applications worldwide. The on-chip Thermal Management
(TMG) feature allows for significantly reduced power
dissipation on the device. The Le5711 device is offered in
space-saving package types, 44-pin eTQFP and 32-pin PLCC.
The small footprint of the SLIC device allows designers to save
board space, increasing the density of lines on the board. The
Le5711 device is also designed to significantly reduce the
number of external components required for linecard design.
Zarlink offers a range of compatible codec/filters that perform
the codec function in a line card. In particular the Legerity
QLSLAC™ device, another member of the VE580 series,
combined with the Le5711 device provides a programmable
line circuit that can be configured for varying requirements.
RELATED LITERATURE
BLOCK DIAGRAM
B
2
A
BGND
(RING)
2
RSN
(TIP)
VTX
HP
080753 Le58QL02/021/031 QLSLAC
080754 Le58QL061/063 QLSLAC
080748 Le5711 Evaluation Board User’s Guide
2
2
2
2
CH2
Interface
CH2
2-W
CH2
and Control
Decoder
CH2
Input
CH2
Document ID# 081132
Rev:
Distribution:
CH2
Common
Bias
D
Public Document
CH1
and Control
Decoder
Input
CH1
VE580 Series
CH1
Data Sheet
Le5711
Date:
Version: 2
Data Sheet
CH1
Interface
CH1
2-W
CH1
Sep 18, 2007
BGND
A
HP
B
RSN
VTX
1
1
(TIP)
1
(RING)
1
1
1

Related parts for le57d111

le57d111 Summary of contents

Page 1

... Device Package 32-pin PLCC (Green), Le57D111DJC 50 dB Reverse Polarity 44-pin eTQFP (Green), Le57D111BTC 50 dB Reverse Polarity 1. The green package meets RoHS Directive 2002/95/EC of the European Council to minimize the environmental impact of electrical equipment. 2. For delivery using a tape and reel packing system, add a "T" suffix to the OPN (Ordering Part Number) when placing an order ...

Page 2

... Ring-Trip Detector Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Loop Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 SLIC Device Decoding User-Programmable Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 DC Feed Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Application Circuit .15 Line card Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Physical Dimensions .17 32-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Revision .19 Revision .19 Revision .19 Revision .19 2 Zarlink Semiconductor Inc. ...

Page 3

... Disconnect SLIC state, which enables the ring-trip detector. leads.* The output of this amplifier is equal to the AC metallic components of the line i pin is more negative than the DAC pin, the DET pin will be i pin becomes more positive than the DAC pin, and the DET i 3 Zarlink Semiconductor Inc. ...

Page 4

... Exposed Pad Zarlink Semiconductor Inc. BGND (RING (TIP DAC 25 VBAT ...

Page 5

... Transmit audio signal of channel 2. This output is a scaled version of the A and B metallic voltage. VTX also sources the two-wire input impedance programming network. 2 The exposed thermal management pad must be in thermal contact with an exposed copper plate with an electrical potential of battery supply (VBAT pin). 5 Zarlink Semiconductor Inc (RING (RING). ...

Page 6

... V – –90 to +12 V (TIP), A (TIP), B (RING), B (RING) ±150 ± –0 1.7 W (see note 1) θ 43ºC/W typ (see note 2) θ 16ºC/W typ (see note 2) JESD22 Class 1C compliant 6 Zarlink Semiconductor Inc BAT BAT + 0 ...

Page 7

... On hook –0.35 300 to 3.4 kHz –0.15 relative to 1 kHz +3 dBm to –55 dBm –0.15 relative to 0 dBm 0 dBm to –37 dBm –0.15 +3 dBm to 0 dBm –0.35 7 Zarlink Semiconductor Inc. Min Typ Max Unit 26 dB Ω –50 +50 mV 2.5 Vpk 1.1 –64 – ...

Page 8

... Both channels, Active state, BAT = –48 V Test Conditions Min f = .01 to 100 MHz HF gen output = 1.5 Vrms AXi BXi 2.2 nF AXi BXi Test Conditions Min –75 –400 8 Zarlink Semiconductor Inc. Typ Max Unit 100 µA +40.3 V Typ Max Unit ...

Page 9

... V BAT Test Conditions (See Note 1) Min network such as that shown in Figure Two-Wire Status Disconnect 0 1 Active Polarity Reversed 1 1 (Le57D111 devices only Standby 9 Zarlink Semiconductor Inc. Typ Max Unit 0.40 V 2.4 Typ Max Unit – −2 V Typ Max ...

Page 10

... 0. Zarlink Semiconductor Inc. Description connected between the VTX and RSN pins. The Ti fuse resistors are R , and Z is the desired 2-wire AC F 2WIN input impedance. When computing Z , the internal Ti current amplifier pole and any external stray capacitance between VTX and RSN must be taken into account ...

Page 11

... -------------- where R AB1 REF 303 Ω 43 – AB2a 3 – AB2b AB2a 111 Ω – 1 – AB3a BAT L ⋅ – 0.33 V AB3b AB3a BAT 11 Zarlink Semiconductor Inc REF ' = 10.8 ...

Page 12

... VTX 2 SLIC V AB AGND RSN (RING RSN log L2 VTX (TIP VTX 2 SLIC AGND RSN (RING RSN log L4 BRS = 20 log Zarlink Semiconductor Inc. R REF ...

Page 13

... SLIC AGND = 600 Ω RSN (RING) RSN Figure 6. RFI Test Circuit C 1 200Ω 50Ω RF 200Ω RF 50Ω Zarlink Semiconductor Inc 120 124 K RX ...

Page 14

... C AX2 2.2 nF TIP A (TIP HP2 100 nF RING B (RING BX2 2 600 Ω LAC LOOP BAT = - 52 V Zarlink Semiconductor Inc AGND/ VCC RSVD 1,2 1,2 DGND Le5711 VTX RSN 1 CDC 1 CH1 1.5 µF DET IREF CAS C 0.33 µF ...

Page 15

... HP2 100 nF R HP2 15 kΩ B (RING BX2 = 600 Ω R ANALOG LAC GROUND LOOP BAT = - Zarlink Semiconductor Inc. V BAT R 20 MΩ R TH1 DAC 1 MΩ DAC TH2 C 909 kΩ TH 100 nF Shared between 4 DSLIC packages ...

Page 16

... TISP6NTP2A SMT 2 MΩ SMT 1.82 MΩ Le5711 device SMT 1.8 kΩ Capacitor (X7R) 330 nF SMT 1 MΩ SMT 909 kΩ SMT 20 MΩ NPN BC639 16 Zarlink Semiconductor Inc. Tol. Rating Comments 20% 100 V 20% 100 ...

Page 17

... Exact shape of this feature is optional. 0.550 0.553 5 Details of pin 1 identifier are optional but must be located -- 10 deg within the zone indicated. 6 Sum of DAM bar protrusions to be 0.007 max per lead. 7 Controlling dimension : Inch. 8 Reference document : JEDEC MS-016 32-Pin PLCC 17 Zarlink Semiconductor Inc. ...

Page 18

... Markings will vary with the mold tool used in manufacturing. Min Nom Max Symbol Min - - 1.20 c 0.09 0.05 - 0.15 L 0.45 0.95 1.00 1. BSC S 0.20 10 BSC b 0.17 12 BSC e 10 BSC D2 0.08 - 0. aaa 0 deg 3.5 deg 7 deg bbb 0 deg - - ccc 11 deg 12 deg 13 deg ddd 11 deg 12 deg 13 deg N 44-Pin eTQFP 18 Zarlink Semiconductor Inc. Nom Max - 0.20 0.60 0.75 1.00 REF - - 0.20 0.27 0.80 BSC 8.00 8.00 0.20 0.20 0.10 0.20 44 ...

Page 19

... Removed non-green OPNs from • Removed Le57D113JC and Le57D113DJC from Revision • Removed Le57D113BTC from Ordering Information, on page Revision • Added new headers/footers due to Zarlink purchase of Legerity on August 3, 2007 Ordering Information, on page 1. Ordering Information, on page 1. 19 Zarlink Semiconductor Inc. 1. ...

Page 20

... I C Standard Specification as defined by Philips. Zarlink, ZL, the Zarlink Semiconductor logo are trademarks, and Legerity, the Legerity logo and combinations thereof are registered trademarks of Zarlink Semiconductor Inc. All other trademarks and registered trademarks are the property of their respective owners. © 2007 Zarlink Semiconductor Inc. All Rights Reserved. ...

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