92hd89f Integrated Device Technology, 92hd89f Datasheet - Page 26
92hd89f
Manufacturer Part Number
92hd89f
Description
Ten Channel Content Protection Hd Audio Codec Low Power Optimized For Ecr15b And Eup
Manufacturer
Integrated Device Technology
Datasheet
1.92HD89F.pdf
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92HD89F
Ten channel Content Protection HD Audio codec optimized for low power
©2009 INTEGRATED DEVICE TECHNOLOGY, INC.
The codec supports the following digital microphone configurations:
Power State DMIC Widget
Digital Mics
D1-D3
D0-D3
D0
D4
D5
0
1
2
3
4
either DMIC_0 or 1
Single Edge on the
one DMIC pin and
second DMIC pin.
Enabled?
Double Edge on
Double Edge on
Data Sample
Double Edge
Single Edge
Yes
Yes
No
-
-
N/A
Clock Disabled
Clock Disabled
Clock Disabled
Clock Disabled
Table 13. DMIC_CLK and DMIC_0,1 Operation During Power State
Clock Capable
DMIC_CLK
Output
ADC Conn.
0, or 1
0, or 1
0, or 1
0, or 1
N/A
Table 12. Valid Digital Mic Configurations
Input Disabled
Input Disabled
Input Disabled
Input Disabled
Input Capable
sampling on a single Digital Mic pin channel on rising edge and second Digital Mic
DMIC_0,1
When using a microphone that supports multiplexed operation (2-mics can share
Requires both DMIC_0 and DMIC_1, External logic required to support sampling
support alternative clock edge (multiplexed output) capability. Two ADC units are
Connected to DMIC_0 and DMIC_1, External logic required to support sampling
support alternative clock edge capability. Two ADC units are required to support
on a single Digital Mic pin channel on rising edge and second Digital Mic right
channel on falling edge of DMIC_CLK for those digital microphones that don’t
on a single Digital Mic pin channel on rising edge and second Digital Mic right
channel on falling edge of DMIC_CLK for those digital microphones that don’t
right channel on falling edge of DMIC_CLK for those digital microphones that
a common data line), configure the microphone for “Left” and select mono
Available on either DMIC_0 or DMIC_1, External logic required to support
don’t support alternative clock edge (multiplexed output) capability.
“Left” D-mic data is used for ADC left and right channels.
26
Input Widget is Enabled. Otherwise, the DMIC_CLK remains Low
DMIC_CLK Output is Enabled when either DMIC_0 or DMIC_1
operation using the vendor specific verb.
Available on either DMIC_0 or DMIC_1
required to support this configuration
DMIC_CLK is HIGH-Z with Weak Pull-down
DMIC_CLK is HIGH-Z with Weak Pull-down
DMIC_CLK is HIGH-Z with Weak Pull-down
DMIC_CLK is HIGH-Z with Weak Pull-down
No Digital Microphones
this configuration
Notes
Notes
V1.0 04/10
92HD89F
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