mt89l86apr1 Zarlink Semiconductor, mt89l86apr1 Datasheet - Page 9

• Manufacturer Part Number: mt89l86apr1
• Description: 512 X 256 Channels 3.3 V Multiple Rate Digital Switch Mrdx With Constant Delay Mode
• Manufacturer: Zarlink Semiconductor

Different Input/Output Data Rates
When Different I/O rate is selected by the DMO bit, the input and output data rates should be selected at the IDR
and ODR bits, respectively. The Switching Configuration Bits (SCB) are ignored with this operation. This selection
allows the user to multiplex conventional 2.048 Mb/s serial streams into two higher rates and vice-versa. In addition
to the rate conversion itself, the MT89L86 allows for a complete 256 x 256 channel non-blocking switch at different
rates. In this operation, the per-channel variable/constant throughput delay selection is provided.
Depending on which data rates are programmed for input and output streams, the number of data streams used on
the input and output as well as the serial interface clock (CLK input pin) is different. Once the CPU defines the data
rates at the IDR and ODR bits, the MT89L86 automatically configures itself with the appropriate number of input
and output streams for the desired operation. Table 2 summarizes the four options available when it is used with
different I/O rates. Figures 21 to 24 show the timing for each of the four modes shown in Table 2.
Input Frame Offset Selection
For the 4.096 and 8.192 Mb/s serial interface data rates, the MT89L86 provides a feature called Input Frame Offset
allowing the user to compensate for the varying delays at the incoming serial inputs while building large switch
matrices. Usually, different delays occur on the digital backbones causing the data and frame synchronization
Input and Output
2 Mb/s to 4 Mb/s
2 Mb/s to 8 Mb/s
4 Mb/s to 2 Mb/s
8 Mb/s to 2 Mb/s
Data Rate
Switching
Interface
(2 Mb/s)
2 Mb/s
2 Mb/s
2 Mb/s
Nibble
4 Mb/s
4 Mb/s
8 Mb/s
Data Rates
Serial
Table 1 - Switching Configurations for Identical Input and Output Data Rate
required at
Interface
CLK Pin
(MHz)
Clock
4.096
4.096
4.096
4.096
4.096
8.192
4.096
Table 2 - Switching Configurations for Different I/O Data Rates
required at
Interface
CLK Pin
(MHz)
Clock
4.096
8.192
4.096
8.192
Number of
Streams
Input x
Output
10x10
16x8
8x8
8x4
8x4
4x4
2x2
x Output
Number
of Input
Streams
8x4
8x2
4x8
2x8
Zarlink Semiconductor Inc.
MT89L86
128x128 Non-Blocking
256x256 Non-Blocking
256x256 Non-Blocking
256x256 Non-Blocking
256x256 Non-Blocking
256x256 Non-Blocking
256x256 Non-Blocking
256x256 Non-Blocking
512x256 Blocking
512x256 Blocking
(only 4-input x 4-output
512x256 Nibbles
Channel Capacity
can be selected)
9
Capacity
Channel
Matrix
Matrix
STi0-7/STo0-3
STi0-7/STo0-1
STi0-3/STo0-7
STi0-1/STo0-7
Streams Used
Input/Output
STi0-15/STo0-7
STi0-7/STo0-7
STi0-9/STo0-9
STi0-7/STo0-3
STi0-7/STo0-3
STi0-3/STo0-3
STi0-1/STo0-1
Input/Output
Streams Used
Delay Selection
throughput
Throughput
Variable/
Constant
Data Sheet
Variable/
Constant
Selection
Yes
Yes
Yes
Yes
Delay
Yes
Yes
Yes
Yes
No
No
No