mt8941bpr1 Zarlink Semiconductor, mt8941bpr1 Datasheet

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... Advanced T1/CEPT Digital Trunk PLL Ordering Information MT8941BE MT8941BP MT8941BPR MT8941BP1 MT8941BPR1 28 Pin PLCC* Description The MT8941B is a dual digital phase-locked loop providing the timing and synchronization signals for the T1 or CEPT transmission links and the ST-BUS. The first PLL provides the T1 clock (1.544 MHz) synchronized to the input frame pulse at 8 kHz ...

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... DPLL #1 which is also connected internally to DPLL #2. MT8941B VDD RST CVb MS1 6 Yo F0i F0b Ai 9 MS2 MS3 10 C16i ENC2o 11 ENC4o C2o C2o C4b Figure 2 - Pin Connections Description 2 Zarlink Semiconductor Inc. Data Sheet CVb MS3 19 ENC2o 28 PIN PLCC ...

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... Figures 9-13) must be a minimum of five times the rise time of the power supply. In normal operation, the RST pin must be held low for a minimum of 60 nsec to reset the device (+5 V) Power supply Connection. 5, 18, 25 MT8941B Description (pin 16). C2o (pin 16). C2o 3 Zarlink Semiconductor Inc. Data Sheet (pin 1). CV ...

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... P12 P12 t = 512 K T H0 P16 P16 t = 766 K T CSF P16 is the 12.352 MHz master clock oscillator period P12 is the 16.384 MHz master clock period P16 Figure 4 - Phase Comparison 4 Zarlink Semiconductor Inc. Data Sheet Output (1.544 MHz / 2.048 MHz) region ...

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... These signals are 4.096 MHz (C4o and C4b) and 2.048 MHz (C2o and C2o) clocks, and the 8 kHz frame pulse (F0b) derived from the 16.384 MHz master clock. This mode can be the same as the FREE- RUN mode if the C8Kb pin is tied to V MT8941B Zarlink Semiconductor Inc. Data Sheet ...

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... Provides CEPT/ST-BUS timing signals locked to the falling edge of the 8 kHz internal signal CLOCK-1 provided by DPLL # SINGLE Provides CEPT/ST-BUS timing signals locked to the falling edge of the 8 kHz internal signal CLOCK-2 provided by DPLL #1. Table 2 - Major Modes of DPLL #2 Zarlink Semiconductor Inc. Function Function 6 Data Sheet ...

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... C8Kb. Minor modes of DPLL #2 The minor modes for DPLL #2 depends upon the status of the mode select bits MS2 and MS3 (pins 7 and 17). MT8941B Functional Description Table 3 - Minor Modes of DPLL #2 7 Zarlink Semiconductor Inc. Data Sheet ...

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... Same as mode ‘0’. SINGLE CLOCK-2 MODE: F0b is an input but has no function in this mode. Same as mode 2. SINGLE CLOCK-2 MODE: Provides the CEPT/ST-BUS compatible timing signals locked to the 8 kHz internal signal provided by DPLL #1. 8 Zarlink Semiconductor Inc. Data Sheet DPLL #2 ...

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... Output X: “don’t care” input. Connect Zarlink Semiconductor Inc. Data Sheet CVb (MHz) o:1.544 o:1.544 o:1.544 o:1.544 i:1.544 i:1.544 i:1.544 i:1.544 o:1.544 o:1.544 o:1.544 o:1.544 i:2.408 i:2.408 i:2.408 i:2.408 SS. ...

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... Range” for recommended oscillator tolerances for DPLL #1 & #2. Table 6 - Lock-in Range vs. Oscillator Frequency Tolerance Figure 5 - The Spectrum of the Inherent Jitter for either PLL MT8941B Lock-in Range (HHz) DPLL #1 5 2.55 10 2.51 20 2.43 32 2.33 50 2.19 100 1.79 150 1.39 175 1.19 10 Zarlink Semiconductor Inc. Data Sheet DPLL #2 1.91 1.87 1.79 1.69 1.55 1.15 .75 .55 ...

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... DPLL #1 will be equal to that of the DPLL #2 oscillator when DPLL #2 is free-running. In this case, the oscillator tolerance of DPLL #1 has no impact on its output clock tolerance. For this reason recommended to use a H32 ppm oscillator for DPLL #2 and a H100 ppm oscillator for DPLL #1. MT8941B 11 Zarlink Semiconductor Inc. Data Sheet ...

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... Centralized Timing 8 kHz Reference Signal M U MT8941B X Clocks 8 kHz Reference Signal Figure 8 - Application Differences between the MT8940 and MT8941B MT8941B Data Bus Line Card 1 MT8940 Line Card n MT8940 Data Bus 12 Zarlink Semiconductor Inc. Data Sheet Clocks Clocks Line Card 1 Line Card n ...

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... MHz clock, while DPLL #2 (in FREE-RUN mode) uses the 16.384 MHz crystal oscillator to generate the ST-BUS clocks for system timing. The generated ST-BUS signals can be used to synchronize the system and the switching equipment at the master end. MT8941B 13 Zarlink Semiconductor Inc. Data Sheet ...

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... C2i C4b F0i E8Ko C2o F0b RST Mode of Operation for the MT8941B DPLL #1 - NORMAL (MS1= DPLL #2 - NORMAL (MS0=0; MS1=0; MS2=1; MS3= Zarlink Semiconductor Inc. Data Sheet MT8980/81 ST-BUS SWITCH DSTi DSTo CSTi CSTo TxT TRANSMIT T1 TxR LINK (1.544 Mbps) ...

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... MT8941B MT8941B V DD MH89790B C4b C2i F0i C2o F0b Y o RST V DD DPLL #1 - NOT USED R C DPLL #2 - FREE-RUN 15 Zarlink Semiconductor Inc. Data Sheet MT8980/81 ST-BUS SWITCH DSTi DSTo CSTi0 CSTi1 CSTo OUTA CEPT TRANSMIT PRIMARY OUTB MULTIPLEX DIGITAL RxT LINK RECEIVE ...

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... CV E8Ko F0b C4o C2o Y o RST Mode of Operation for the MT8941B V DPLL #1 - NOT USED DPLL #2 - NORMAL (MS0=0; MS1=0; MS2=1; MS3=1) 16 Zarlink Semiconductor Inc. Data Sheet MT8980/81 ST-BUS SWITCH DSTi DSTo CSTi0 CSTi1 CSTo OUTA CEPT TRANSMIT PRIMARY OUTB MULTIPLEX DIGITAL ...

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... Voltages are with respect to ground (V ‡ Sym. Min. Typ. Max. V 4.5 5 Zarlink Semiconductor Inc. Data Sheet MT8941B V MS0 DD MS1 MS2 C4o MS3 F0i C4b ST-BUS C12i EN CV C8Kb C2o TIMING C16i EN C4o C2o SIGNALS EN C2o Ai ...

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... -100 - 120 IL I -10 + Zarlink Semiconductor Inc. Data Sheet Test Conditions Under clocked condition, with the inputs tied to the same supply rail as the corresponding pull-up /down resistors =2 =0 ...

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... Max. Units C8HH C8LL ICHL ICLH 19 Zarlink Semiconductor Inc. Data Sheet (Refer to Figure 14) Test Conditions Load Load (Refer to Figure 15) Test Conditions Load Load % In Divide -1 Mode % In Divide - 2 Mode ns ...

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... C4o 42LH t 42HL V OH C2o W2oL V OH C2o V OL Figure 16 - Timing Information on DPLL #2 Outputs MT8941B Figure 15 - DPLL #1 in DIVIDE Mode t WFP t FPH t fC4 t t 4oLH 4oHL t P2o t W2oH t fC2 t 2oLH 20 Zarlink Semiconductor Inc. Data Sheet t P4o t rC4 t rC2 t 2oHL ...

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... W2oH t 238 244 W2oL t 6 rC2 t 6 fC2 2oLH 2oHL 21 Zarlink Semiconductor Inc. Data Sheet (Refer to Figure 16) Test Conditions Load Load Load 85 pF Load Load Load ns ns ...

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... Sym. Min. Typ. Max. t 244 WFP t 244 P4o Zarlink Semiconductor Inc. Data Sheet (Refer to Figure 14) Max. Units Test Conditions For DPLL #1, while ns operating to provide the T1 clock signal. For DPLL #2, while operating to provide the ns CEPT and ST-BUS timing signals ...

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... Min. Typ. Max. Units t 16 PHZ t 12 PLZ t 11 PZH PZL PZL 10% t PZH 90% Outputs Disabled 23 Zarlink Semiconductor Inc. Data Sheet (Refer to Figure 19) Test Conditions Load Load Load Load 3.0 V 2.7 V 1.3 V 0.3 V 1.3 V 1.3 V Outputs Enabled ...

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... Timing is over recommended temperature & power supply voltages. G ‡ Typical figures are and are for design aid only: not guaranteed and not subject to production testing. MT8941B ‡ Sym. Min. Typ. Max PLH t 15 PHL 24 Zarlink Semiconductor Inc. Data Sheet Units Test Conditions Load Load ...

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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...