zl30100 Zarlink Semiconductor, zl30100 Datasheet - Page 12

• Manufacturer Part Number: zl30100
• Description: T1/e1 System Synchronizer
• Manufacturer: Zarlink Semiconductor

3.3
The TIE corrector circuit eliminates phase transients on the output clock that may occur during reference switching
or the recovery from Holdover mode to Normal mode.
On the recovery from Holdover mode (dependent on the HMS pin) or when switching to another reference input,
the TIE corrector circuit measures the phase delay between the current phase (feedback signal) and the phase of
the selected reference signal. This delay value is stored in the TIE corrector circuit. This circuit creates a new virtual
reference signal that is at the same phase position as the feedback signal. By using the virtual reference, the PLL
minimizes the phase transient it experiences when it switches to another reference input or recovers from Holdover
mode.
C20: 20 MHz master clock on OSCi
C20: 20 MHz master clock on OSCi
Time Interval Error (TIE) Corrector Circuit
C20 Clock Accuracy
C20 Clock Accuracy
+32 ppm
-32 ppm
+50 ppm
-50 ppm
0 ppm
0 ppm
Figure 5 - DS1 Mode Out-of-Range Limits (OOR_SEL=0)
Figure 6 - E1 Mode Out-of-Range Limits (OOR_SEL=1)
-200
-200
-180
-150
-150
-150
-130
-115
-100
-100
-100
-96
-83
-80
Zarlink Semiconductor Inc.
-64
-51
-50
-50
-50
C20
-50
C20
-32
ZL30100
-32
C20
C20
0
0
0
0
0
0
0
0
12
C20
32
32
C20
50
50
50
50
64
51
80
83
100
96
100
100
115
130
150
150
150
180
200
200
Out of Range
Out of Range
In Range
Out of Range
In Range
Out of Range
In Range
In Range
Out of Range
In Range
Out of Range
In Range
Frequency offset [ppm]
Frequency
Offset [ppm]
Data Sheet