zl30102 Zarlink Semiconductor, zl30102 Datasheet
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... Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2004-2005, Zarlink Semiconductor Inc. All Rights Reserved. T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110 ZL30102QDG ZL30102QDG1 64 pin TQFP* Trays, Bake & Drypack • Provides Lock, Holdover and selectable Out of Range indication • ...
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... The ZL30102 DS1/E1 Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization for DS1/E1 transmission equipment deploying redundant network clocks. The ZL30102 generates ST-BUS and other TDM clock and framing signals that are phase locked to one of three network references or to another system master-clock reference. It helps ensure system reliability by monitoring its references for frequency accuracy and stability and by maintaining a tight phase alignment between the primary master-clock and secondary master clock outputs even in the presence of high network jitter ...
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... Time Interval Error (TIE 5.11 Maximum Time Interval Error (MTIE 5.12 Phase Continuity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.13 Lock Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.0 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.1 Power Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.2 Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.2.1 Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.2.2 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.3 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.4 Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.5 Clock Redundancy System Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.0 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.1 AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 ZL30102 Table of Contents 3 Zarlink Semiconductor Inc. Data Sheet ...
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... Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 ZL30102 Table of Contents 4 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 23 - Timing Parameter Measurement Voltage Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 24 - REF0/1/2 Input Timing and Input to Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 25 - REF2_SYNC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure Output Timing Referenced to F8/F32o Figure 27 - DS1 Output Timing Referenced to F8/F32o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 28 - DS2 Output Timing Referenced to F8/F32o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 ZL30102 List of Figures 5 Zarlink Semiconductor Inc. Data Sheet ...
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... Input to output timing for REF0, REF1 and REF2 references when TIE_CLR = 0 (see Figure 24).“ 40 Section 7.1 45 Section 7.2 ZL30102 Change Changed description for hitless reference switching. Removed power supply decoupling circuit and included reference to synchronizer power supply decoupling application note. Change Specified clock and frame pulse outputs forced to high ...
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... SEC_MSTR OOR_SEL TIE_CLR FASTLOCK 64 Figure 2 - Pin Connections (64 pin TQFP, please see Note 1) Note 1: The ZL30102 uses the TQFP shown in the package outline designated with the suffix QD, the ZL30102 does not use the e-Pad TQFP. ZL30102 ZL30102 ...
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... Hitless Mode Switching (Input). The HMS input controls phase accumulation during the transition from Holdover or Freerun mode to Normal mode on the same reference. A logic low at this pin will cause the ZL30102 to maintain the delay stored in the TIE corrector circuit when it transitions from Holdover or Freerun mode to Normal mode. A logic high ...
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... Analog Ground C4/C65o Clock 4.096 MHz or 65.536 MHz (Output). This output is used for ST-BUS operation at 2.048 Mbit/s, 4.096 Mbit/s or 65.536 MHz (ST-BUS 65.536 Mbit/s). The output frequency is selected via the OUT_SEL pin, see Table 3 on page 19. ZL30102 Description nominal DC nominal DC ...
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... One of five possible frequencies may be used: 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz or 16.384 MHz. This pin is internally pulled down to GND. 56 REF1 Reference (Input). See REF0 pin description. 57 REF2 Reference (Input). See REF0 pin description. ZL30102 Description nominal DC nominal DC 10 Zarlink Semiconductor Inc. Data Sheet ...
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... Reference Select Multiplexer (MUX) The ZL30102 accepts three simultaneous reference input signals and operates on their rising edges. One of them, the primary reference (REF0), the secondary reference (REF1) or the tertiary reference (REF2) signal is selected as input to the TIE Corrector Circuit based on the Reference Selection (REF_SEL1:0) inputs. ...
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... The single cycle and coarse frequency failures must be absent for let the timer re-qualify the input reference signal as valid. Multiple failures of less than 2.5 s each have an accumulative effect and will disqualify the reference eventually. This is illustrated in Figure 4 where REF0 experiences disruptions while REF1 is stable. ZL30102 OR REF_OOR OR ...
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... If there no other reference available, it stays in Holdover mode. The precise frequency monitor’s failure thresholds are selected with the OOR_SEL input based on the ZL30102 applications, Table 1. Figure 5 and Figure 6 show the out of range limits for various master clock accuracies. It will take the precise frequency monitor qualify or disqualify the input reference ...
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... This delay value is stored in the TIE corrector circuit. This circuit creates a new virtual reference signal that is at the same phase position as the feedback signal. By using the virtual reference, the PLL minimizes the phase transient it experiences when it recovers from Holdover mode. ZL30102 C20 -130 ...
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... Normal mode. This causes accumulation of phase in network elements. In both cases the PLL’s output can be aligned with the input reference by setting TIE_CLR low. Regardless of the HMS pin state, reference switching in the ZL30102 is always hitless unless TIE_CLR is kept low continuously. ...
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... Phase = 0.1 ppm 200 ns holdover_drift - Phase = mode_change = 10 x (200 ns) = 2.13 µs - Phase 10 changes ZL30102 REF Output Clock REF Output Clock REF Output Clock TIE_CLR=0 REF Output ...
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... Digital Phase Lock Loop (DPLL) The DPLL of the ZL30102 consists of a phase detector, a limiter, a loop filter and a digitally controlled oscillator as shown in Figure 10. The data path from the phase detector to the limiter is tapped and routed to the lock detector that provides a lock indication which is output at the LOCK pin. ...
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... As shown in Figure 1, the state machine controls the TIE Corrector Circuit and the DPLL. The control of the ZL30102 is based on the inputs MODE_SEL1:0, REF_SEL1:0 and HMS. 3.7 Master Clock The ZL30102 can use either a clock or crystal as the master timing source. For recommended master timing circuits, see the Applications - Master Clock section. ZL30102 18 Zarlink Semiconductor Inc ...
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... REF1 or REF2). These signals are available in two groups controlled by the OUT_SEL pin, see Table 3. OUT_SEL 0 1 Table 3 - Clock and Frame Pulse Selection with OUT_SEL Pin ZL30102 Applicable Standard ANSI T1.403 Telcordia GR-1244-CORE Stratum 4/4E ITU-T G.703 ETSI ETS 300 011 ...
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... ZL30102 is in Holdover mode may result in an additional offset (over the 0.1 ppm) in frequency accuracy of ± 1 ppm. Which is much greater than the 0.1 ppm of the ZL30102. The other factor affecting the accuracy is large jitter on the reference input prior to the mode switch. ZL30102 ...
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... DPLL to recover from Holdover via one of two paths depending on the logic level at the HMS pin (see Figure 11). If HMS=0 then the ZL30102 will transition directly to Normal mode and it will align its output signals with its input reference (see Figure 9). If HMS=1 then the ZL30102 will transition to Normal mode via the TIE correction state and the phase difference between the output signals and the input reference will be maintained ...
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... In the manual modes of operation (MODE_SEL1:0 ≠ 11) the active reference input (REF0, REF1 or REF2) is selected by the REF_SEL1 and REF_SEL0 pins as shown in Table 5. When the logic value of the REF_SEL pins is changed when the DPLL is in Normal mode, the ZL30102 will perform a hitless reference switch. REF_SEL1 ...
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... If both references fail then the ZL30102 enters the Holdover mode without switching to another reference. When the ZL30102 comes out of reset or when REF2 is the current reference when the ZL30102 is put in the Automatic mode, then REF0 has priority over REF1. Otherwise there is no preference for REF0 or REF1 which is referred to as non-revertive reference selection ...
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... REF_SEL outputs indicate that the device has remained locked to the old reference. However the LOCK pin is de-asserted, the lock-qualify timer is reset, and the LOCK pin remains de-asserted for the full lock-time duration. See 7.2, “Performance Characteristics“ on page 44 for lock-time duration. ZL30102 Normal (HOLDOVER=0) ...
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... Where the new reference has enough frequency offset and/or TIE-corrected phase offset to force the output outside the phase-lock-window, the LOCK output will de- assert, the lock-qualify timer is reset, and LOCK will stay de-asserted for the full lock-time duration. Figure 16 illustrates this process. ZL30102 10 s REF1 Lock Time 25 Zarlink Semiconductor Inc ...
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... Therefore the redundant signals must closely track the active signals. The ZL30102 supports this kind of clock redundancy in various ways; • Lock only to the active clock. The ZL30102 uses the 922 Hz loop filter bandwidth to closely track the active clock, even in the presence of jitter on the active clock. However the active and redundant frame pulse may not be aligned. ...
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... REF2_SYNC input. The REF2_SYNC pulse must be generated from the clock that is present on the REF2 input. The ZL30102 checks the number of REF2 cycles in the REF2_SYNC period. If this is not the nominal number of cycles, the REF2_SYNC pulse is considered invalid. For example, if REF2 is a 8.192 MHz clock and REF2_SYNC kHz frame pulse, then there must be exactly 1024 REF2 cycles in a REF2_SYNC period ...
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... The HOLDOVER and REF_FAIL pins help evaluate quality of clocks and quality of redundant clock. ZL30102 OSC REF0 Output Clocks REF1 ZL30102 REF2 REF2_SYNC Redundant Frame Sync (optional) Redundant Clock Active Clock Active Frame Sync (optional) REF2_SYNC REF2 ZL30102 REF0 Output Clocks REF1 OSC 28 Zarlink Semiconductor Inc. Data Sheet ...
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... REF2 and REF2_SYNC as the input reference, REF_SEL1=1 The ZL30102 allows for the switch from Secondary Master mode to Primary Master mode with no frequency or phase hits on the output clocks. The switch from Primary Master mode to Secondary Master mode may introduce a phase transient on the output clocks as the TIE correction circuit is disabled to allow the Secondary master device to track the active clocks closely ...
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... Holdover accuracy is defined as the absolute accuracy of an output clock signal, when it is not locked to an external reference signal, but is operating using storage techniques. For the ZL30102, the storage value is determined while the device is in Normal Mode and locked to an external reference signal. ...
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... Although a short lock time is desirable not always possible to achieve due to other synchronizer requirements. For instance, better jitter transfer performance is achieved with a lower frequency loop filter which increases lock time. And better (smaller) phase slope performance (limiter) results in longer lock times. ZL30102 31 Zarlink Semiconductor Inc. ...
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... Tolerance 3 Rise & fall time 4 Duty cycle Table 7 - Typical Clock Oscillator Specification The output clock should be connected directly (not AC coupled) to the OSCi input of the ZL30102, and the OSCo output should be left open as shown in Figure 19. ZL30102 ZL30102 20 MHz as required < 40% to 60% +3 ...
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... Table 8 - Typical Crystal Oscillator Specification ZL30102 6.3 Power Up Sequence The ZL30102 requires that the 3.3 V supply is not powered up after the 1.8 V supply. This is to prevent the risk of latch-up due to the presence of parasitic diodes in the IO pads. Two options are given: 1. Power-up the 3.3 V supply fully first, then power up the 1.8 V supply 2 ...
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... A simple power up reset circuit with about a 60 µs reset low time is shown in Figure 21. Resistor R only and limits current into the RST pin during power down conditions. The reset low time is not critical but should be greater than 300 ns. ZL30102 ZL30102 +3 kΩ ...
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... Timing for these types of systems can be generated by the ZL30102 which supports primary/secondary master timing protection switching. The architecture shown in Figure 22 is based on the ZL30102 being deployed on two separate timing cards; the primary master timing card and the secondary master timing card. In normal operation the primary master timing card receives synchronization from the network and provides timing for the whole system ...
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... OSCi = Clock, OUT_SEL=0 3 OSCi = Clock, OUT_SEL=1 4 Core supply current with: OSCi = OSCi = Clock 6 Schmitt trigger Low to High threshold point 7 Schmitt trigger High to Low threshold point 8 Input leakage current 9 High-level output voltage ZL30102 Symbol Min. V -0.5 DD_R V -0.5 CORE_R V -0.5 PIN V -0.3 OSC I PIN T -55 ...
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... MHz reference period 6 reference pulse width high or low * Supply voltage and operating temperature are as per Recommended Operating Conditions. * Period Min/Max values are the limits to avoid a single-cycle fault detection. Short-term and long-term average periods must be within Out-of- Range limits. ZL30102 Sym. Min. Max. Units V ...
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... Supply voltage and operating temperature are as per Recommended Operating Conditions. * See Figure 17, “Examples of REF2 & REF2_SYNC to Output Alignment” on page 27 for further explanation. REF2 REF2_SYNC Note: REF2 can be 1.544 MHz, 2.048 MHz, 8.192 MHz or 16.384 MHz. REF2_SYNC is 8 kHz. ZL30102 t REF<xx> REFW REFW t REF< ...
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... MHz reference input to F8/F32o delay 6 8.192 MHz reference input to C8o delay 7 8.192 MHz reference input to F8/F32o delay 8 16.384 MHz reference input to C16o delay 9 16.384 MHz reference input to F8/F32o delay * Supply voltage and operating temperature are as per Recommended Operating Conditions. ZL30102 Symbol t REF8kD t REF1.5D t REF1.5_F8D t REF2D ...
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... F65o pulse with low 18 F65o delay 19 C65o pulse width low 20 C65o delay 21 Output clock and frame pulse rise time 22 Output clock and frame pulse fall time * Supply voltage and operating temperature are as per Recommended Operating Conditions. ZL30102 Sym. Min. Max. t -0.4 0.3 C2D t 243.0 244.1 C2L t 243 ...
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... F8o C2o F4o C4o C8o F16o C16o F32o C32o F65o C65o F32o, C32o, F65o and C65o are drawn on a larger scale than the other waveforms in this diagram. Figure Output Timing Referenced to F8/F32o ZL30102 t C2L t F4L t C4L t C8L t C16L t C32L t C65L 41 Zarlink Semiconductor Inc ...
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... C6o pulse width low 3 Output clock and frame pulse rise time 4 Output clock and frame pulse fall time * Supply voltage and operating temperature are as per Recommended Operating Conditions. F8_32o C6o Figure 28 - DS2 Output Timing Referenced to F8/F32o ZL30102 Sym. Min. Max. t -0.6 0.6 C1.5D t 323.1 324 ...
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... AC Electrical Characteristics* - OSCi 20 MHz Master Clock Input Characteristics 1 Oscillator Tolerance - DS1 2 Oscillator Tolerance - E1 3 Duty cycle 4 Rise time 5 Fall time * Supply voltage and operating temperature are as per Recommended Operating Conditions. ZL30102 Min. Max. Units -32 +32 ppm -50 +50 ppm Zarlink Semiconductor Inc ...
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... Switching from Normal mode to Holdover mode 13 Switching from Holdover mode to Normal mode Output Phase Slope 14 primary master mode 15 secondary master mode * Supply voltage and operating temperature are as per Recommended Operating Conditions. ZL30102 Min. Max. Units 0.1 ppm 0 ppm Determined by stability of the 20 MHz master clock oscillator 0 ...
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... Limit in limit in the UI filter time domain 0. Zarlink Semiconductor Inc. Data Sheet Interface DS1 Line timing, DS1 External timing 2048 kbit/s ZL30102 maximum jitter Units generation 45.3 0. 324 0. ZL30102 maximum jitter Units generation 7.92 0. ZL30102 maximum jitter Units generation 24.4 0. ...
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... C6o (6.312 MHz) 6 C8o (8.192 MHz) 7 C16o (16.384 MHz) 8 C32o (32.768 MHz) 9 C65o (65.536 MHz) 10 F4o (8 kHz) 11 F8o (8 kHz) 12 F16o (8 kHz) 13 F32o (8 kHz) 14 F65o (8 kHz) * Supply voltage and operating temperature are as per Recommended Operating Conditions. ZL30102 Max. Notes [ 0.45 0.47 0.53 0.42 0.58 0.42 0.56 0.46 0.49 0.43 0.43 0.44 0.43 0.46 46 Zarlink Semiconductor Inc. ...
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... Zarlink Semiconductor 2002 All rights reserved. ISSUE ACN DATE APPRD. Package Code Previous package codes ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...