zl30108 Zarlink Semiconductor, zl30108 Datasheet
zl30108
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zl30108 Summary of contents
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... The ZL30108 output clock’s wander and jitter generation are compliant with GR-253-CORE OC-3 and G.813 STM-1 specifications. LOCK ...
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... Time Interval Error (TIE 6.9 Maximum Time Interval Error (MTIE 6.10 Phase Continuity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.11 Phase Lock Time 7.0 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.1 Power Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.2 Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.2.1 Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.2.2 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.3 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.4 Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.0 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.1 AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.2 Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 ZL30108 Table of Contents 2 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 9 - Mode Switching in Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 10 - Clock Oscillator Circuit Figure 11 - Crystal Oscillator Circuit Figure 12 - Power-Up Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 13 - Timing Parameter Measurement Voltage Levels Figure 14 - Input to Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 15 - SONET/SDH Output Timing Referenced to F8ko . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 ZL30108 List of Figures 3 Zarlink Semiconductor Inc. Data Sheet ...
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... RST pin 20 Section 7.4 21 Table “DC Electrical Characteristics*“ 25 Table “Performance Characteristics* - Functional“ ZL30108 Change Updated Ordering Information. Change Changed description for hitless reference switching. Removed power supply decoupling circuit and included reference to synchronizer power supply decoupling application note. Change Specified clock and frame pulse outputs forced to high impedance ...
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... Physical Description 2.1 Pin Connections AGND REF_SEL REF0 REF1 OOR_SEL TIE_CLR Figure 2 - Pin Connections (32 pin QFN) ZL30108 ZL30108 (E-pad Zarlink Semiconductor Inc. Data Sheet GND OSCi OSCo RST ...
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... Multi Frame Pulse (Output). This is a CMOS 2 kHz active high 51 ns framing pulse, which marks the beginning of a multi frame. This clock output pad includes a Schmitt triggered input which serves as a PLL feedback path; proper transmission-line termination should be applied to maintain reflections below Schmitt trigger levels. ZL30108 Description nominal DC nominal. ...
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... TIE Circuit Reset (Input). A logic low at this input resets the Time Interval Error (TIE) correction circuit resulting in a realignment of input phase with output phase Internal Connection. Package E-pad, this pin is internally connected to device GND, it can be left unconnected or it can be connected to GND. ZL30108 Description nominal DC nominal Zarlink Semiconductor Inc ...
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... Reference Select Multiplexer (MUX) The ZL30108 accepts two simultaneous reference input signals and operates on their rising edges. One of two, the primary reference (REF0) or the secondary reference (REF1) signal is selected as input to the TIE Corrector Circuit based on the Reference Selection (REF_SEL) input. ...
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... The precise frequency monitor and the timer do not affect the mode (Holdover/Normal) of the DPLL. C20i Clock Accuracy 0 ppm -83 +32 ppm -32 ppm -115 -96 -75 -100 Figure 5 - Out-of-Range Thresholds for OOR_SEL=1 ZL30108 SCM or CFM failure 10 s C20 - C20 32 -51 -32 C20 ...
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... Figure 14 and Figure 15. The speed of the phase alignment correction is limited by the loop filter bandwidth. Convergence is always in the direction of least phase travel. TIE_CLR can be kept low continuously. In that case the output clocks will always align with the selected input reference. This is illustrated in Figure 7. ZL30108 C20 -52 ...
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... TIE_CLR = 0 locked to REF0 REF0 REF1 Output Clock locked to REF1 REF0 REF1 Output Clock Figure 7 - Timing Diagram of Hitless Reference Switching ZL30108 TIE_CLR = 1 locked to REF0 REF0 REF1 Output Clock locked to REF1 REF0 REF1 Output Clock 11 Zarlink Semiconductor Inc. Data Sheet ...
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... Digital Phase Lock Loop (DPLL) The DPLL of the ZL30108 consists of a phase detector, an integrated on-chip loop filter, and a digitally controlled oscillator as shown in Figure 8. The data path from the phase detector to the filter is tapped and routed to the lock indicator that provides a lock indication which is output at the LOCK pin. ...
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... Normal Mode. The frequency in the Automatic Holdover mode is calculated from frequency samples stored before the ZL30108 entered the Automatic Holdover mode. This ensures that the coarse frequency monitor and the single cycle monitor have time to disqualify a bad reference before it corrupts the holdover frequency ...
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... Automatic Holdover mode if the currently selected reference is disrupted (see Figure 9). After the power up reset, the ZL30108 will initially go into the Automatic Holdover mode, generating clocks with the same accuracy as it would be in the Freerun mode. If the currently selected reference is not disrupted (see Figure 3), the state machine takes the DPLL out of the Automatic Holdover mode ...
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... ZL30108 is in the Automatic Holdover mode may result in an additional offset (over the 0.01 ppm) in frequency accuracy of ZL30108. The other factor affecting the accuracy is large jitter on the reference input prior ( ms) to the mode switch. ZL30108 ...
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... Reference Selection The active reference input (REF0 or REF1) is selected by the REF_SEL pin as shown in Table 4. If the logic value of the REF_SEL pin is changed when the DPLL is in Normal mode, the ZL30108 will perform a hitless reference switch. REF_SEL (input pin) When the REF_SEL inputs are used to force a change from the currently selected reference to another reference, the action of the LOCK output will depend on the relative frequency and phase offset of the old and new references ...
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... Holdover accuracy is defined as the absolute frequency accuracy of an output clock signal, when it is not locked to an external reference signal, but is operating using storage techniques. For the ZL30108, the storage value is determined while the device is in Normal Mode and locked to an external reference signal. ...
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... Frequency 2 Tolerance 3 Rise & Fall Time 4 Duty Cycle Table 5 - Typical Clock Oscillator Specification The output clock should be connected directly (not AC coupled) to the OSCi input of the ZL30108 and the OSCo output should be left open as shown in Figure 10. ZL30108 20 MHz As required <10 ns 40% to 60% ZL30108 +3 ...
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... Oscillation Mode 4 Resonance Mode 5 Load Capacitance 6 Maximum Series Resistance Table 6 - Typical Crystal Oscillator Specification ZL30108 The 100 Ω resistor and the 1 µH inductor may improve stability and are optional. ZL30108 20 MHz As required Fundamental Parallel As required 50 Ω 20 MHz OSCi 1 MΩ OSCo 100 Ω ...
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... Power Up Sequence The ZL30108 requires that the 3 not powered after the 1.8 V. This is to prevent the risk of latch-up due to the presence of parasitic diodes in the IO pads. Two options are given: 1. Power-up 3.3 V first, 1.8 V later 2. Power up 3.3 V and 1.8 V simultaneously ensuring that the 3.3 V power is never lower than 1.8 V minus a few hundred millivolts (e ...
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... Voltages are with respect to ground (GND) unless otherwise stated. DC Electrical Characteristics* Characteristics 1 Supply current with: OSCi = Core supply current with: OSCi = Schmitt trigger Low to High threshold point 6 Schmitt trigger High to Low threshold point 7 Input leakage current ZL30108 Symbol V DD_R V CORE_R V PIN V OSC I PIN ESD Sym ...
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... Rise and Fall Threshold Voltage Low * Supply voltage and operating temperature are as per Recommended Operating Conditions. * Voltages are with respect to ground (GND) unless otherwise stated. ALL SIGNALS t t IRF, ORF Figure 13 - Timing Parameter Measurement Voltage Levels. ZL30108 Sym. Min. Max 0.4 OL Sym ...
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... MHz reference input to F8ko delay 6 8.192 MHz reference input to F8ko delay 7 16.384 MHz reference input to F8ko delay 8 19.44 MHz reference input to C19o delay 9 19.44 MHz reference input to F8ko delay * Supply voltage and operating temperature are as per Recommended Operating Conditions. ZL30108 Symbol Min. t 483 REF2kP t 120 REF8kP t 338 REF1 ...
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... F8ko pulse width high 7 Output clock and frame pulse rise or fall time (with 30 pF load) * Supply voltage and operating temperature are as per Recommended Operating Conditions. F8ko C19o F2ko Figure 15 - SONET/SDH Output Timing Referenced to F8ko ZL30108 t t REFW REFW t REF<xx> REF8D REF< ...
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... Hz Filter Output Phase Continuity (MTIE) 11 Reference switching 12 Switching from Normal mode to Automatic Holdover mode 13 Switching from Automatic Holdover mode to Normal mode * Supply voltage and operating temperature are as per Recommended Operating Conditions. ZL30108 Sym. Min. Typ. Max. -20 +20 -32 + Min ...
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... Option 2 ITU-T G.813 Limit in Equivalent limit UI in time domain ( 6.4 ns) 0.1 UI 0.64 pp 0.5 UI 3.22 pp 0.1 UI 0.64 pp Max. [ 0.5 0.5 0.5 26 Zarlink Semiconductor Inc. Data Sheet T1.105.03 conformance ZL30108 Maximum Jitter Units Generation 0. 0. rms 0. ZL30108 Maximum Jitter Generation Units Notes ...
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... Zarlink Semiconductor 2003 All rights reserved ISSUE 3 ACN CDCA CDCA CDCA 30-01-2004 15-08-2005 DATE 22-08-2005 APPRD. Package Code Previous package codes ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...