zl30101 Zarlink Semiconductor, zl30101 Datasheet
zl30101
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zl30101 Summary of contents
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... HMS Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2004-2006, Zarlink Semiconductor Inc. All Rights Reserved. T1/E1 Stratum 3 System Synchronizer ZL30101QDC ZL30101QDG1 64 Pin TQFP* Trays, Bake & Drypack • External master clock source: clock oscillator or crystal Applications • ...
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... The ZL30101 Stratum 3 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization for multi-trunk T1 and E1 transmission equipment. The ZL30101 generates ST-BUS and other TDM clock and framing signals that are phase locked to one of two input references. It helps ensure system reliability by monitoring its references for accuracy and stability and by maintaining stable output clocks during reference switching operations and during short periods when a reference is unavailable ...
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... Time Interval Error (TIE 5.11 Maximum Time Interval Error (MTIE 5.12 Phase Continuity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.13 Lock Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.0 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.1 Power Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.2 Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.2.1 Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.2.2 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.3 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.4 Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.0 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.1 AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.2 Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 ZL30101 Table of Contents 3 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 9 - Mode Switching in Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 10 - Reference Switching in Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 11 - Clock Oscillator Circuit Figure 12 - Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 13 - Power-Up Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 14 - Timing Parameter Measurement Voltage Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 15 - Input to Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 16 - Output Timing Referenced to F8/F32o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 ZL30101 List of Figures 4 Zarlink Semiconductor Inc. Data Sheet ...
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... Table “Pin Description“ 11 Section 3.2 16 Section 3.4 20 Section 4.4 21 Section 5.0 ZL30101 Change Updated Ordering Information Change Added description for hitless reference switching. Removed power supply decoupling circuit and included reference to synchronizer power supply decoupling application note. Change Specified clock and frame pulse outputs forced to high ...
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... Table “Performance Characteristics*: Output Jitter Generation - ITU-T G.812 Conformance“ 33 Table “Performance Characteristics* - Unfiltered Intrinsic Jitter“ ZL30101 Change Corrected time-constant of example reset circuit Corrected package power rating Corrected current consumption Corrected input voltage characteristics to reflect Schmitt trigger Corrected input leakage current to reflect internal pull-ups ...
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... TIE_CLR BW_SEL 64 Figure 2 - Pin Connections (64 pin TQFP, please see Note 1) Note 1: The ZL30101 uses the TQFP shown in the package outline designated with the suffix QD, the ZL30101 does not use the e-Pad TQFP. ZL30101 ZL30101 2 ...
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... ZL30101 to maintain the delay stored in the TIE Corrector Circuit when it transitions from Holdover or Freerun mode to Normal mode. A logic high on this pin will cause the ZL30101 to measure a new delay for its TIE Corrector Circuit thereby minimizing the output phase movement when it transitions from Holdover or Freerun mode to Normal mode ...
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... Analog Ground AGND Analog Ground C4/C65o Clock 4.096 MHz or 65.536 MHz (Output). This output is used for ST-BUS operation at 2.048 Mbps, 4.096 Mbps or 65.536 MHz (ST-BUS 65.536 Mbps). The output frequency is selected via the OUT_SEL pin. ZL30101 Description nominal. DC nominal. DC nominal. DC nominal. ...
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... MHz, 8.192 MHz or 16.384 MHz. This pin is internally pulled down to GND internal bonding Connection. Leave unconnected. 57 REF1 Reference (Input). See REF0 pin description internal bonding Connection. Leave unconnected. ZL30101 Description nominal. DC nominal Zarlink Semiconductor Inc. Data Sheet ...
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... Reference Select Multiplexer (MUX) The ZL30101 accepts two simultaneous reference input signals and operates on their rising edges. One of them, the primary reference (REF0) or the secondary reference (REF1) signal can be selected as input to the TIE corrector circuit based on the reference selection (REF_SEL) input. ...
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... When the incoming signal returns to normal (REF_FAIL=0), the DPLL returns to Normal mode with the output signal locked to the input signal. Each of the monitors has a built-in hysteresis to prevent flickering of the REF_FAIL status pin at the threshold boundaries. The precise frequency monitor and the timer do not affect the mode (Holdover/Normal) of the DPLL. ZL30101 OR dis/requalify timer OR REF_DIS= reference disrupted ...
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... BW_SEL=0. Convergence is always in the direction of least phase travel. In general the TIE correction should not be exercised when Holdover mode is entered for short time periods. TIE_CLR can be kept low continuously. In that case the output clocks will always be aligned with the selected input reference. This is illustrated in Figure 6. ZL30101 C20 -12 -9 ...
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... Normal mode. This causes accumulation of phase in network elements. In both cases the PLL’s output can be aligned with the input reference by setting TIE_CLR low. Regardless of the HMS pin state, reference switching in the ZL30101 is always hitless unless TIE_CLR is kept low continuously. ZL30101 ...
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... Phase = ns) = 330 ns 10 changes where: - 0.01 ppm is the accuracy of the Holdover mode - the maximum phase discontinuity in the transition from the Normal mode to the Holdover mode ZL30101 HMS = 1 REF Output Clock REF Output Clock REF Output Clock ...
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... Digital Phase Lock Loop (DPLL) The DPLL of the ZL30101 consists of a phase detector, a limiter, a loop filter, a digitally controlled oscillator (DCO) and a lock indicator, as shown in Figure 8. The data path from the phase detector to the limiter is tapped and routed to the lock indicator that provides a lock indication which is output at the LOCK pin. ...
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... As shown in Figure 1, the control state machine controls the TIE Corrector Circuit and the DPLL. The control of the ZL30101 is based on the inputs MODE_SEL1:0, REF_SEL and HMS. 3.7 Master Clock The ZL30101 can use either a clock or crystal as the master timing source. For recommended master timing circuits, see the Applications - Master Clock section. ZL30101 17 Zarlink Semiconductor Inc ...
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... Control and Modes of Operation 4.1 Loop Filter Selection The loop filter settings can be selected through the BW_SEL pin, see Table 1. For the ZL30101 to be compliant with Telcordia GR-1244-CORE Stratum 3, BW_SEL must be set low. BW_SEL Detected REF Frequency 1.544 MHz, 2.048 MHz, 8 ...
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... DPLL to recover from Holdover via one of two paths depending on the logic level at the HMS pin (see Figure 9). If HMS=0 then the ZL30101 will transition directly to Normal mode and it will align its output signals with its input reference (see Figure 7). If HMS=1 then the ZL30101 will transition to Normal mode via the TIE correction state and the phase difference between the output signals and the input reference will be maintained ...
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... Reference Selection The active reference input (REF0, REF1) is selected by the REF_SEL pin as shown in Table 4. If the logic value of the REF_SEL pin is changed when the DPLL is in Normal mode, the ZL30101 will perform a hitless reference switch. REF_SEL When the REF_SEL inputs are used to force a change from the currently selected reference to another reference, the action of the LOCK output will depend on the relative frequency and phase offset of the old and new references ...
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... Since intrinsic jitter is always present, jitter attenuation will appear to be lower for small input jitter signals than for large ones. Consequently, accurate jitter transfer function measurements are usually made with large input jitter signals (for example 75% of the specified maximum tolerable input jitter). ZL30101 REF0 REF1 ...
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... Holdover accuracy is defined as the absolute accuracy of an output clock signal, when it is not locked to an external reference signal, but is operating using storage techniques. For the ZL30101, the storage value is determined while the device is in Normal Mode and locked to an external reference signal. ...
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... Power Supply Decoupling Jitter levels on the ZL30101 output clocks may increase if the device is exposed to excessive noise on its power pins. For optimal jitter performance, the ZL30101 device should be isolated from noise on power planes connected to its 3.3 V and 1.8 V supply pins. For recommended common layout practices, refer to Zarlink Application Note ZLAN-178 ...
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... The output clock should be connected directly (not AC coupled) to the OSCi input of the ZL30101, and the OSCo output should be left open as shown in Figure 11. ZL30101 6.2.2 Crystal Oscillator Alternatively, a crystal oscillator may be used. A complete oscillator circuit made crystal, resistor and capacitors is shown in Figure 12. The Telcordia GR1244-CORE Stratum 3 requirements for holdover stability and freerun accuracy may not be met with this crystal oscillator circuit ...
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... ZL30101 6.3 Power Up Sequence The ZL30101 requires that the 3.3 V rail is not powered-up later than the 1.8 V rail. This is to prevent the risk of latch-up due to the presence of parasitic diodes in the IO pads. Two options are given: 1. Power up the 3.3 V rail fully first, then power up the 1.8 V rail 2 ...
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... A simple power up reset circuit with about a 60 µs reset low time is shown in Figure 13. Resistor R only and limits current into the RST pin during power down conditions. The reset low time is not critical but should be greater than 300 ns. ZL30101 ZL30101 +3 kΩ ...
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... Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. * Voltages are with respect to ground (GND) unless otherwise stated. Recommended Operating Conditions* Characteristics 1 Supply voltage 2 Core supply voltage 3 Operating temperature * Voltages are with respect to ground (GND) unless otherwise stated. ZL30101 Symbol Min. V -0.5 DD_R V -0.5 CORE_R V -0.5 ...
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... Rise and fall threshold voltage low * Supply voltage and operating temperature are as per Recommended Operating Conditions. * Voltages are with respect to ground (GND) unless otherwise stated. ALL SIGNALS t t IF, OF Figure 14 - Timing Parameter Measurement Voltage Levels ZL30101 Sym. Min. Max. Units I 3.0 6.5 DDS ...
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... MHz reference input to F8/F32o delay 8 16.384 MHz reference input to C16o delay 9 16.384 MHz reference input to F8/F32o delay * Supply voltage and operating temperature are as per Recommended Operating Conditions. t REF<xx>P REF0/1 output clock with the same frequency as REF F8_32o ZL30101 Symbol t REF8KP t REF1.5P t REF2P t REF8P t REF16P t ...
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... F65o pulse with low 20 F65o delay 21 C65o pulse width low 22 C65o delay 23 Output clock and frame pulse rise time 24 Output clock and frame pulse fall time * Supply voltage and operating temperature are as per Recommended Operating Conditions. ZL30101 Sym. Min. Max. t 323.1 323.7 C1.5L t -0.6 0.6 C1.5D t 243.2 243 ...
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... C1.5o C2o F4o C4o F8o C8o F16o C16o F32o C32o F65o C65o F32o, C32o, F65o and C65o are drawn on a larger scale than the other waveforms in this diagram. Figure 16 - Output Timing Referenced to F8/F32o ZL30101 t C1.5L t C2L t F4L t C4L t C8L t C16L t C32L t C65L 31 Zarlink Semiconductor Inc ...
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... Reference switching 10 Switching from Normal mode to Holdover mode 11 Switching from Holdover mode to Normal mode Output Phase Slope 12 1.8 Hz Filter and 922 Hz Filter * Supply voltage and operating temperature are as per Recommended Operating Conditions. ZL30101 Sym. Min. Max. Units -4.6 4.6 ppm ...
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... G.812 ITU-T Jitter Generation Requirements Jitter Equivalent Limit in limit in the UI filter time domain 0. Max. [ns 0.45 0.47 0.42 0.42 0.56 0.46 0.49 0.40 0.33 0.43 0.36 0.42 33 Zarlink Semiconductor Inc. Data Sheet ZL30101 maximum jitter Units generation 45.3 0. 324 0. ZL30101 maximum jitter Units generation 24.4 0. Notes ] pp ...
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... Zarlink Semiconductor 2002 All rights reserved. ISSUE ACN DATE APPRD. Package Code Previous package codes ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...