zl30112 Zarlink Semiconductor, zl30112 Datasheet - Page 10

• Manufacturer Part Number: zl30112
• Description: Slic/codec Dpll
• Manufacturer: Zarlink Semiconductor

5.10
This is the time it takes the PLL to phase lock to the input signal. Phase lock occurs when the input signal and
output signal are aligned in phase with respect to each other within a certain phase distance (not including jitter).
Lock time is affected by many factors which include:
•
•
•
•
The presence of input jitter makes it difficult to define when the PLL is locked as it may not be able to align its output
to the input within the required phase distance, dependent on the PLL bandwidth and the input jitter amplitude and
frequency.
Although a short lock time is desirable, it is not always possible to achieve due to other synchronizer requirements.
For instance, better jitter transfer performance is achieved with a lower frequency loop filter which increases lock
time. See Section 7.2, “Performance Characteristics“ for Maximum Phase Lock Time.
6.0
This section contains ZL30112 application specific details for power supply decoupling, clock and crystal operation,
reset operation, and control operation.
6.1
Jitter levels on the ZL30112 output clocks may increase if the device is exposed to excessive noise on its power
pins. For optimal jitter performance, the ZL30112 device should be isolated from noise on power planes connected
to its 3.3 V and 1.8 V supply pins. For recommended common layout practices, refer to Zarlink Application Note
ZLAN-178.
6.2
The ZL30112 can use either a clock or crystal as the master timing source. Zarlink Application Note ZLAN-68 lists a
number of applicable oscillators and crystals that can be used with the ZL30112.
6.2.1
When selecting a Clock Oscillator, numerous parameters must be considered. These includes absolute frequency,
frequency change over temperature, output rise and fall times, output levels, duty cycle and phase noise.
initial input to output phase difference
initial input to output frequency difference
PLL loop filter bandwidth
in-lock phase distance
Power Supply Decoupling
Master Clock
Applications
Phase Lock Time
Clock Oscillator
1
2
3
4
Table 1 - Typical Clock Oscillator Specification
Frequency
Tolerance
Rise & Fall Time
Duty Cycle
Zarlink Semiconductor Inc.
ZL30112
10
20 MHz
As required
<10 ns
40% to 60%
Data Sheet