zl30136 Zarlink Semiconductor, zl30136 Datasheet - Page 4

• Manufacturer Part Number: zl30136
• Description: Gbe And Telecom Rate Network Interface Synchronizer
• Manufacturer: Zarlink Semiconductor

APLL Loop Filter
JTAG and Test
Master Clock
Pin #
G4
G2
G3
D2
D1
C2
E2
H2
A5
B5
C5
H3
H4
H5
F2
cs_b/asel0
filter_ref0
filter_ref1
apll_filter
i2c_en
Name
si/sda
trst_b
int_b
osco
osci
tms
tdo
tck
so
tdi
Type
I/O
I/B
O
I
O
I
O
I
I
I
O
A
A
A
I
I
u
u
u
u
u
Serial Interface Input (LVCMOS). Serial interface data pin. When i2c_en = 0,
this pin acts as the si pin for the serial interface. When i2c_en = 1, this pin acts as
the sda pin (bidirectional) for the I
Serial Interface Output (LVCMOS). Serial interface data output. When i2c_en =
0, this pin acts as the so pin for the serial interface. When i2c_en = 1, this pin is
unused and should be left unconnected.
Chip Select for SPI/Address Select 0 for I
pin acts as the chip select pin (active low) for the serial interface. When i2c_en =
1, this pin acts as the asel0 pin for the I
Interrupt Pin (LVCMOS). Indicates a change of device status prompting the
processor to read the enabled interrupt service registers (ISR). This pin is an
open drain, active low and requires an external pulled-up to Vdd.
I
low the SPI interface is enabled. Internally pull-up to Vdd.
External Analog PLL Loop Filter Terminal.
Analog PLL External Loop Filter Reference.
Analog PLL External Loop Filter Reference.
Test Serial Data Out (Output). JTAG serial data is output on this pin on the
falling edge of tck. This pin is held in high impedance state when JTAG scan is
not enabled.
Test Serial Data In (Input). JTAG serial test instructions and data are shifted in
on this pin. This pin is internally pulled up to Vdd. If this pin is not used then it
should be left unconnected.
Test Reset (LVCMOS). Asynchronously initializes the JTAG TAP controller by
putting it in the Test-Logic-Reset state. This pin should be pulsed low on power-
up to ensure that the device is in the normal functional state. This pin is internally
pulled up to Vdd. If this pin is not used then it should be connected to GND.
Test Clock (LVCMOS): Provides the clock to the JTAG test logic. If this pin is not
used then it should be pulled down to GND.
Test Mode Select (LVCMOS). JTAG signal that controls the state transitions of
the TAP controller. This pin is internally pulled up to V
then it should be left unconnected.
Oscillator Master Clock Input (LVCMOS). This input accepts a 20 MHz
reference from a clock oscillator (XO) or crystal XTAL. The stability and accuracy
of the clock at this input determines the free-run accuracy and the long term
holdover stability of the output clocks.
Oscillator Master Clock Output (LVCMOS). This pin must be left unconnected
when the osci pin is connected to a clock oscillator.
2
C Interface Enable (LVCMOS). If set high, the I
Zarlink Semiconductor Inc.
ZL30136
4
2
Description
C interface.
2
C interface.
2
C (LVCMOS). When i2c_en = 0, this
2
C interface is enabled, if set
Short Form Data Sheet
DD
. If this pin is not used