zl30131 Zarlink Semiconductor, zl30131 Datasheet - Page 8

• Manufacturer Part Number: zl30131
• Description: Oc-192/stm-64 Sonet/sdh/10gbe Network Interface Synchronizer
• Manufacturer: Zarlink Semiconductor

2.0
The ZL30131 OC-192/STM-64 PDH/SONET/SDH/10GbE Network Interface Synchronizer is a highly integrated
device that provides timing for both PDH/SONET/SDH and Ethernet network interface cards. A functional block
diagram is shown in Figure 1.
This device is ideally suited for designs that require both a transmit timing path (backplane to PHY) and a receive
timing path (PHY to backplane). Each path is controlled with separate DPLLs (Tx DPLL, Rx DPLL) which are both
independently configurable through the serial interface (SPI or I
in Figure 2. In this application, the ZL30131 translates the 19.44 MHz clock from the telecom rate backplane
(system timing bus), translates the frequency to 622.08 MHz or 156.25 MHz for the PHY Tx clock, and filters the
jitter to ensure compliance with the related standards. A programmable synthesizer (P0) provides synchronous
PDH clocks with multiples of 8 kHz for generating PDH interface clocks. On the receive path, the Rx DPLL and the
P1 synthesizer translate the line recovered clock (8 kHz or 25 MHz) from the PHY to the 19.44 MHz telecom
backplane (line recovered timing) for the central timing cards. The ZL30131 allows easy integration of Ethernet line
rates with today’s telecom backplanes.
Functional Description
Central
ZL30121
Timing
19.44 MHz
Card
Line Card
8 kHz
OC-192
P
DPLL
P1
Rx
P
S
ZL30131
1.544 MHz
Figure 2 - Typical Application of the ZL30131
P0
S
A
PHY
P
DPLL
DPLL
APLL
BITS A
Tx
622.08 MHz
A
19.44 MHz
Line Recovered Timing
B
System Timing Bus
Zarlink Semiconductor Inc.
ZL30131
XOVER
11
156.25 MHz
19.44 MHz
BITS B
B
2
B
DPLL
C). A typical application of the ZL30131 is shown
APLL
DPLL
Tx
PHY
P S
A
ZL30131
P0
1.544 MHz
S
S
DPLL
Line Card
Rx
P1
10GbE
25 MHz
19.44 MHz
P
ZL30121
Central
Timing
Short Form Data Sheet
Card
Backplane
Telecom