APPLICATIONS
FEATURES
The information in this document is Preliminary and may be changed in whole or in part without notice. Zarlink
makes no guarantee that the device(s) described herein will ever be considered for commercialization or mass
production. If you are considering using the proposed device(s) or doing any related design work, please call
a Zarlink sales representative for current information.
Voice enabled Cable and DSL Modems
Residential VoIP Gateways and Routers
Media Terminal Adapters (MTA)
Fiber to the User/Premise/Home (FTTH/P/H), Fiber in
the Loop (FITL) Optical Network Terminals (ONT)
Wireless Local Loop (WLL), PBX, ISDN NT1/TA
Complete BORSCHT function for 2 channels in a single
VoicePort™ chipset
— Battery Feed, Over-voltage support, integrated Ringing,
Integrated Power Management
— Integrated high voltage switching regulator controllers
— Low power Idle and On-hook transmission states
Worldwide Programmability
— Two-wire AC impedance, Balance Impedance, Gain
— DC feed voltage and current limit
— Ringing frequency, voltage and current limit
— 12 kHz and 16 kHz Metering
— Programmable loop closure and ring trip thresholds
Ringing
— 5 REN
— Up to 140-Vpk internal balanced sinusoidal or
— Unbalanced ringing for PBX trunk compatibility
Powerful signal generator
— Universal Caller ID generation
— Up to 4 simultaneous tones
— Automatic cadencing feature
VoicePath™ API-II Software available to implement
FXS functions
— Supports chipset calibration
— Line configuration via VoicePath Profile Wizard
VeriVoice™ Test Suite Subscriber Loop Test
— Seamless integration with API-II software
— Utilizes integrated self test capabilities
— Line fault detection and reporting
Pin selectable PCM/MPI or GCI interface
G.711 µ-law, A-law, or 16 bit linear coding
Wideband 16 kHz sampling mode
Integrated 150 mW 3-V Relay Driver
Small footprint chipset
— 64-pin TQFP and exposed pad 24-pin QFN
NOTE: On August 3, 2007, Zarlink Semiconductor acquired the products and technology of Legerity Holdings.
line Supervision, Codec, Hybrid (2W/4W), Test
trapezoidal ringing with programmable DC offset
– Wide input voltage range (VSW =+3.3V to +35 V)
– Switching power supply tracks line voltage
minimizing active & ringing state power dissipation
Dual Channel Tracking Battery Wideband VoicePort™ Chipset
Standalone & Embedded
ORDERING INFORMATION
1.
2.
DESCRIPTION
Zarlink's dual channel VE8820 Tracking Battery VoicePort™
chipset implements a dual-channel telephone line interface by
providing all the necessary voice interface functions from the
high voltage subscriber line to the µP/DSP digital interface.
This chipset reduces system level cost, space, and power.
Designers benefit by having a simple, cost effective, low-power
and dense, interface design without sacrificing features or
functionality. The programmable, feature rich VoicePort chipset
provides a highly functional line interface which meets the
requirements of short and medium loop (up to 1500 Ohms
total) applications. Features include: high voltage switching
regulator, self-test, line test capabilities, integrated ringing (up
to 140-Vpk), worldwide software programmability with
wideband capability, flexible signal generator with tone
cadencing, caller ID generation and all BORSCHT functions.
These VoicePort chipset features are crucial for designing
cost-effective, full-featured Voice over Broadband solutions.
VOICEPORT™ CHIPSET BLOCK DIAGRAM
Le88506DVC
Le88830KQC
Device OPN
RINGD
RINGD
TIPD
TIPD
The green package meets RoHS Directive 2002/95/EC of the
European Council to minimize the environmental impact of
electrical equipment.
For delivery using a tape and reel packing system, add a “T” suffix
to the OPN (Ordering Part Number) when placing an order.
1
1
2
2
VBA T
VBA T
Driver
Driver
Tip &
Tip &
Ring
Line
Ring
Line
Le88830
SLIC
Shifting
Shifting
Level
Buffer
Buffer
Level
64-pin 10 x 10 TQFP (Green)
24-pin 6 x 6 QFN (Green)
SWCMPY
SWCMPZ
SWOUTY
SWOUTZ
SWVSY
SWVSZ
SWISY
SWISZ
VREFS
VREFS
RDC
RDC
TDC
TA C
RA C
RA C
TA C
TDC
TFLT
ILSN
IRSN
IRSN
ILSN
TFLT
RTV
RTV
IBO
IBT
IBR
IBR
IBT
IBO
1
1
1
1
1
1
2
2
2
2
2
2
1
1
2
2
1
1
1
2
2
2
Document ID# 130207
Version:
Distribution:
1
2
Package Type
Channel
Interface
Channel
Interface
Switching
Regulator
Controller
Switching
Regulator
Controller
Driver
Driver
Line
Line
1
2
1
NDA Required
Audio Processing
Line Diagnostics
Input Impedance
Line Diagnostics
Hybrid Balance
Le88506 SLAC
FSK or DTMF
Call Progress
FSK or DTMF
Call Progress
Gain Control
Supervision
Loop Detect
Fault Detect
Equalization
Supervision
Loop Detect
Fault Detect
Generation
Generation
Signaling
Signaling
Ring Trip
Ring Trip
DC Feed
Caller ID
DC Feed
Caller ID
Ringing
Ringing
Tone
Tone
1
VE880 Series
VE8820
1
Date:
Microprocessor
PCM Interface
and Time Slot
Input / Output
Conditioning
Packing
Reference
Interface
Assigner
A nalog
(MPI)
and
PLL
Tray
Tray
Sep 18, 2008
2
™
IREF
VREF
LFC
IHL
LFC
IHL
DCLK
DIN
DOUT
CS
INT
RST
PCLK
FS
DXA
DRA
I/O1
I/O2
I/O1
I/O2
1
2
1
2
1
1
2
2