mt9092apr1 Zarlink Semiconductor, mt9092apr1 Datasheet - Page 19

• Manufacturer Part Number: mt9092apr1
• Description: Fully Featured Digital Telephone Circuit With Embedded Hdlc Transceiver And Dsp For Tone Generations And Hands Free Operation
• Manufacturer: Zarlink Semiconductor

The data streams operate at 2048 kb/s and are Time Division Multiplexed into 32 identical channels of 64 kb/s
bandwidth. Frame Pulse (a 244 nSec low going pulse) is used to parse the continuous serial data streams into the
32 channel TDM frames. Each frame has a 125 µSecond period translating into an 8 kHz frame rate. Valid frame
pulse occurs when F0i is logic low coincident with a falling edge of C4i. C4i has a frequency (4096 MHz) which is
twice the data rate. This clock is used to sample the data at the 3/4 bit-cell position on DSTi and to make data
available on DSTo at the start of the bit-cell. C4i is also used to clock the HPhone-II internal functions (i.e., DSP,
Filter/CODEC, HDLC) and to provide the channel timing requirements.
The HPhone-II uses only the first 4 channels of the 32 channel frame. These channels are always defined,
beginning with the first channel after frame pulse, as shown in Figure 7 (DSTi and DSTo channel assignments).
Channels are enabled independantly by the four control bits Ch
(address15h).
Ch
Ch
DATA 1
Receive
DATA 1 or DATA 2
Transmit
SCLK
CS
0
1
➀
➁
➂
➃
➄
EN - D-Channel
EN - C-Channel
operation, only the first two bits (LSB's) of the octet are required; the remaining six bits of the D-Channel
octet carry no information and are tri-stated. When CH
When low, DSTo is forced to logic 0 for the two least significant bit positions.
always routed to the HDLC block regardless of this control bit's logic state.
bandwidth is available and is assigned according to which transceiver is being used. Consult the data
sheet for the selected transceiver for its bit definitions and order of bit transfer. When this bit is high
register data is transmitted on DSTo. When low, this timeslot is tri-stated on DSTo. Receive C-Channel
data (DSTi) is always routed to the register regardless of this control bit's logic state. C-channel data is
transferred on the ST-BUS MSB first by the HPhone-II.
Channel 0 conveys the D-Channel HDLC information. Since this function is dedicated to 16 kb/s
Channel 1 conveys the control/status information for Zarlink’s layer 1 transceiver. The full 64 kb/s
➁
Delays due to MCS-51 internal timing which are transparent.
The HPhone-II: -latches received data on the falling edge of SCLK
The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The subsequent
byte is always data followed by CS returning high.
A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.
The COMMAND/ADDRESS byte contains:
➂
D
0
COMMAND/ADDRESS
D
1
D
2
-outputs transmit data on the falling edge of SCLK
D
3
D
4
D
5
D
6
➄
D
7
1 bit - Read/Write
6 bits - Addressing Data
1 bit - Not used, write logic "0"
Figure 6 - Serial Port Relative Timing
➀
D
0
Zarlink Semiconductor Inc.
D
0
D
DATA INPUT/OUTPUT
1
D
MT9092
1
D
2
D
2
D
19
3
D
3
D
4
D
4
D
0
0
5
D
En -Ch
EN is high, HDLC data is transmitted on DSTo.
5
D
6
D
D
6
0
D
7
7
3
D
En residing in the Timing Control Register
7
➃
➀
A
➂
5
D
0
D
A
0
4
➃
D
1
COMMAND/ADDRESS
D
1
D
A
2
D
3
2
D
3
D
Incoming DSTi data is
A
3
D
2
4
D
4
D
A
5
D
1
5
D
Data Sheet
6
D
6
A
D
0
7
D
7
R/W
D
0