zl50011 Zarlink Semiconductor, zl50011 Datasheet - Page 52

• Manufacturer Part Number: zl50011
• Description: Flexible 512 Channel Dx With On-chip Dpll
• Manufacturer: Zarlink Semiconductor

15 - 8,
6 - 5,
4 - 3
External Read/Write Address: 030
Bit
15
Internal Read/Write Address: 00030
Reset Value: 0000
0
2.
7
1
0
14
0
P_REFSEL
FREERUN
FP1 - FP0
Unused
Name
PINV
13
0
H
12
0
Reserved. In normal functional mode, these bits MUST be set to zero.
REF Input Inversion: When this bit is low, the REF input will not be inverted. When
this bit is high, the REF input will be inverted.
REF Frequency Selection Bits: These bits are used to specify the nominal clock
frequency of the REF input.
When the P_REFSEL bit is high to select the internal 8 kHz signal (derived from the
FPi and CKi inputs) as reference, these bits must be set to 00.
Reference Source Selection Bit: This bit is used to select the reference input to the
DPLL from between two sources. When this bit is low, the reference is from the REF
pin. When this bit is high, the reference is from the internal 8 kHz generated from the
FPi and CKi inputs. When this bit is high, the FP1-0 bits must be set to 00.
If the internal 8 kHz signal is selected as the reference, the user must ensure that the
FPi and CKi input signals will be re-applied after the internal 8 kHz signal is lost (or
failed). If FPi or CKi is not presented to the device, the device cannot accept STi0-15
input data.
Freerun Control Bit: When this bit is low and bit 14 of the Control Register is low, the
DPLL is in Master mode. When this bit is high and bit 14 of the Control Register is low,
the DPLL is in Freerun mode. This bit has no effect when bit 14 of the Control Register
is high.
Table 21 - DPLL Operation Mode (DOM) Register Bits
H
11
0
10
0
H
FP1
0
0
1
1
9
0
Zarlink Semiconductor Inc.
ZL50011
FP0
0
1
0
8
0
1
52
PINV
Reserved
7
8kHz (REF or CKi/FPi)
Description
6
0
1.544 MHz
2.048 MHz
Reference
5
0
FP1
4
FP0
3
2
0
P REF
Data Sheet
1
FREE
0