zl50010 Zarlink Semiconductor, zl50010 Datasheet
zl50010
Manufacturer Part Number
zl50010
Description
Flexible 512 Channel Dx With Enhanced Dpll
Manufacturer
Zarlink Semiconductor
Datasheet
1.ZL50010.pdf
(87 pages)
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Features
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512 channel x 512 channel non-blocking switch
at 2.048 Mbps, 4.096 Mbps or 8.192 Mbps
operation
Rate conversion between the ST-BUS inputs and
ST-BUS outputs
Integrated Digital Phase-Locked Loop (DPLL)
meets Telcordia GR-1244-CORE Stratum 4
enhanced specifications
DPLL provides automatic reference switching,
jitter attenuation, holdover and free run functions
Per-stream ST-BUS input with data rate selection
of 2.048 Mbps, 4.096 Mbps or 8.192 Mbps
Per-stream ST-BUS output with data rate
selection of 2.048 Mbps, 4.096 Mbps or
8.192 Mbps; the output data rate can be different
than the input data rate
Per-stream high impedance control output for
every ST-BUS output with fractional bit
advancement
Per-stream input channel and input bit delay
programming with fractional bit delay
STi0-15
SEC_REF
PRI_REF
CKi
FPi
Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08
OSC
S/P Converter
Input Timing
Copyright 2003-2006, Zarlink Semiconductor Inc. All Rights Reserved.
DPLL
Figure 1 - ZL50010 Functional Block Diagram
APLL
V
Zarlink Semiconductor Inc.
DD
Connection Memory
Data Memory
Flexible 512 Channel DX with Enhanced
Microprocessor
V
1
Registers
SS
Interface
Internal
and
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ZL50010/QCC 160 Pin LQFP
ZL50010/GDC 144 Ball LBGA
ZL50010QCG1 160 Pin LQFP*
ZL50010GDG2 144 Ball LBGA** Trays, Bake & Drypack
Per-stream output channel and output bit delay
programming with fractional bit advancement
Multiple frame pulse outputs and reference clock
outputs
Per-channel constant throughput delay
Per-channel high impedance output control
Per-channel message mode
Per-channel Pseudo Random Bit Sequence
(PRBS) pattern generation and bit error detection
Control interface compatible to Motorola non-
multiplexed CPUs
Connection memory block programming
capability
IEEE-1149.1 (JTAG) test port
3.3 V I/O with 5 V tolerant input
RESET
**Pb Free Tin/Silver/Coppoer
Ordering Information
Output HiZ Control
P/S Converter
Output Timing
*Pb Free Matte Tin
Test Port
-40°C to +85°C
ODE
Trays
Trays
Trays, Bake & Drypack
FPo0
CKo0
CKo2
STo0-15
FPo1
CKo1
STOHZ0-15
FPo2
IC0 - 4
CLKBYPS
Data Sheet
ZL50010
DPLL
April 2006