zl50021 Zarlink Semiconductor, zl50021 Datasheet - Page 73

• Manufacturer Part Number: zl50021
• Description: Enhanced 4 K Digital Switch With Stratum 3 Dpll
• Manufacturer: Zarlink Semiconductor

Note: LDT should be calculated as per the maximum expected amplitude of jitter on the active input reference
using the following formula:
Example: If maximum expected jitter amplitude on 2.048 MHz reference is 10UI (i.e., 10 x 488.2 ns = 4882 ns)
(assuming the jitter frequency where DPLL attenuation is big), the LDT should be programmed to be (4882/15.2)
x 2 = 642 = 0282
External Read/Write Address: 0047
External Read/Write Address: 0048
Reset Value: 000F
15 - 0
Reset Value: 2C00
15 - 0
Bit
Bit
LDT
LDI
15
15
15
15
LDT
LDI
14
14
14
14
LDT15 - 0
LDI15 - 0
Name
Name
H
H
LDT
LDI
13
13
13
13
H
LDT
Lock Detect Threshold Bits: The binary value of these bits defines the upper limit of the
absolute phase from the phase detector output for lock detection.
When the value of the absolute phase is less than or equal to LDT for duration of time
defined by the LDIR register, the DPLL locks.
When the value of the absolute phase is greater than LDT for duration of time defined by
the LDIR register divided by 256, the DPLL does not lock.
Lock Detector Interval Bits: The binary value of these bits defines the time interval that
the output phase detector must be below the lock detect threshold to declare lock.
Unsigned representation of the LDI bits is defined in 4ms intervals.
LDI
12
12
12
12
Table 36 - Lock Detector Threshold Register (LDTR) Bits
Table 37 - Lock Detector Interval Register (LDIR) Bits
H
H
LDT
LDI
11
11
11
11
LDT
LDI
10
10
10
10
LDT = MAX_EXP_JITTER (ns) x 2
LDT
LDI
9
9
9
9
Zarlink Semiconductor Inc.
ZL50021
LDT
LDI
15.2 (ns)
8
8
8
8
73
LDT
LDI
7
7
7
7
Description
Description
LDT
LDI
6
6
6
6
LDT
LDI
5
5
5
5
LDT
LDI
4
4
4
4
LDT
LDI
3
3
3
3
LDT
LDI
2
2
2
2
Data Sheet
LDT
LDI
1
1
1
1
LDT
LDI
0
0
0
0