zl50020 Zarlink Semiconductor, zl50020 Datasheet - Page 63

• Manufacturer Part Number: zl50020
• Description: Enhanced 2 K Channel Tdm Switch With Rate Conversion
• Manufacturer: Zarlink Semiconductor

† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to produc-
tion testing.
AC Electrical Characteristics
Note 1:
Note 2:
10 Data hold after DS rising
12 Acknowledgement hold time.
13 DTA drive high to HiZ
11 Acknowledgement delay time.
1
2
3
4
5
6
7
8
9
CS
DS
R/W
A0-A13
D0-D15
DTA
CS de-asserted time
DS de-asserted time
CS setup to DS falling
R/W setup to DS falling
Address setup to DS falling
CS hold after DS rising
R/W hold after DS rising
Address hold after DS rising
Data setup to DTA Low
From DS low to DTA low:
From DS high to DTA high
Registers
Memory
High impedance is measured by pulling to the appropriate rail with R
A delay of 500 µs to 2 ms (see Section 13.2 on page 33) must be applied before the first microprocessor access is
discharge C
performed after the RESET pin is set high.
Characteristics
L
.
Figure 20 - Motorola Non-Multiplexed Bus Timing - Read Access
†
t
t
DSD
CSD
- Motorola Non-Multiplexed Bus Mode - Read Access
Sym.
t
t
t
t
t
t
t
t
t
t
RWS
RWH
CSD
DSD
CSH
t
t
Zarlink Semiconductor Inc.
CSS
t
DHZ
AKD
AKH
AKZ
AS
AH
DS
t
t
AS
CSS
t
RWS
ZL50020
Min.
15
15
10
63
0
5
0
0
0
8
7
4
Typ.
VALID ADDRESS
t
AKD
‡
L
, with timing corrected to cancel time taken to
t
DS
Max.
185
75
12
VALID READ DATA
8
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
DHZ
t
t
RWH
t
AH
C
C
(Note 1)
C
C
C
(Note 1)
CSH
L
L
L
L
L
t
AKH
Test Conditions
= 50 pF
= 50 pF, R
= 50 pF
= 50 pF
= 50 pF, R
t
AKZ
Data Sheet
V
V
V
V
V
V
CT
CT
CT
CT
L
L
CT
CT
= 1 K
= 1 K
2