zl50051gag2 Zarlink Semiconductor, zl50051gag2 Datasheet - Page 45

• Manufacturer Part Number: zl50051gag2
• Description: 8 K Channel Digital Switch With High Jitter Tolerance, Single Rate 8 Or 16 Mbps And 64 Input And 64 Output Streams
• Manufacturer: Zarlink Semiconductor

13.5
Addresses 0083
Thirty-two Local Output Advancement Registers (LOAR0 to LOAR31) allow users to program the output
advancement for output data streams LSTo0 to LSTo31. The possible adjustment is -2 (15 ns), -4 (31 ns) or -6
(46 ns) cycles of the internal system clock (131.072 MHz).
The LOAR0 to LOAR31 registers are configured as follows:
13.5.1
The binary value of these two bits indicates the amount of offset that a particular stream output can be advanced
with respect to the output frame boundary. When the advancement is 0, the serial output stream has the normal
alignment with the generated frame pulse FP8o.
(where n = 0 to 31)
Local Output Advancement Registers (LOAR0 to LOAR31)
Local Output Advancement Bits 1-0 (LOA1-LOA0)
LOARn Bit
15:2
1:0
H
to 00A2
Table 20 - Local Output Advancement (LOAR) Programming Table
Table 19 - Local Output Advancement Register (LOAR) Bits
H
Local Output Advancement
.
Clock Rate 131.072 MHz
-2 cycles (~15 ns)
-4 cycles (~31 ns)
-6 cycles (~46 ns)
0 (Default)
Reserved
LOA[1:0]
Name
Zarlink Semiconductor Inc.
ZL50051/3
Reset
Value
0
0
45
Reserved
Must be set to 0 for normal operation
Local Output Advancement Value
LOA1
Advancement Bits
0
0
1
1
Corresponding
Description
LOA0
0
1
0
1
Data Sheet