zl50075 Zarlink Semiconductor, zl50075 Datasheet - Page 52

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zl50075

Manufacturer Part Number
zl50075
Description
32 K Channel Digital Switch With High Jitter Tolerance, Rate Conversion Per Group Of 2 Streams 8, 16, 32 Or 64 Mbps , And 64 Inputs And 64 Outputs
Manufacturer
Zarlink Semiconductor
Datasheet

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AC Electrical Characteristics
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
No.
10
12
11
1
2
3
4
5
6
7
8
9
Characteristics are over recommended operating conditions unless other wise stated.
All of these specifications refer to ST-BUS inputs and outputs with clock source set to CKi.
Typical figures are at 25°C, V
subject to production testing.
Loads on all serial outputs set to 30 pF.
High Impedance is measured by pulling to the appropriate rail with R
C
CKi to CKo Positive edge
Propagation Delay
CKi to CKo Negative edge
Propagation Delay
STi to posedge CKi setup
STi to posedge CKi hold
STi to negedge CKi setup
STi to negedge CKi hold
Posedge CKi to Output Data Valid
Negedge CKi to Output Data Valid
Posedge CKi to Output Data
tri-state
Negedge CKi to Output Data
tri-state
ODE to Output Data tri-state
ODE to Output Data Enable
L
.
Characteristic (Figure 14)
1
- Serial Data Timing
DD_CORE
at 1.8 V and V
t
t
Zarlink Semiconductor Inc.
Sym.
t
t
t
t
t
t
t
t
CKDP
CKDN
t
t
SINH
SIPS
SIPH
SINS
SIPV
SINV
SINZ
SIPZ
SOE
SOZ
ZL50075
DD_IO
2
to CKi
Min.
-0.8
-0.8
52
3.5
4.1
4.5
5.9
5.9
4.8
4.1
5.8
4.5
4.3
4.6
5.3
5.7
4.5
5
6
at 3.3 V and are for design aid only: not guaranteed and not
Typ.
L
, with timing corrected to cancel time taken to discharge
3
Max.
10.1
13.7
12.9
14.8
14.6
14.5
13.6
11.6
9.2
9.2
13
10
11
15
20
8
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CKo clock source =
CKi
CKo Clock source =
Internal 131 MHz
APLL output
CKo clock source =
CKi
CKo Clock source =
Internal 131 MHz
APLL output
SToA
SToB
SToA
SToB
SToA
SToB
SToA
SToB
SToA
C
SToB
C
SToA
SToB
L
L
= 30 pF, R
= 30 pF, R
5
5
5
5
5
5
5
5
5
5
Notes
Data Sheet
L
L
4
= 1 K
= 1 K
5
5

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