zl50070 Zarlink Semiconductor, zl50070 Datasheet

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... CKi2-0 CK_SEL1-0 Timing FPo3-0 CKo3-0 Figure 1 - ZL50070 Functional Block Diagram Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2004-2006, Zarlink Semiconductor Inc. All Rights Reserved Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of ...

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... In this way it is possible to provide rate conversion from input data channel to output data channel. The ZL50070 uses a master clock (CKi0) and frame pulse (FPi0) to define the TDM data stream frame boundary and timing. A high speed system clock is derived internally from CKi0 and FPi0. The input and output data streams can independently reference their timings to one of the input clocks or to the internal system clock ...

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... Microprocessor Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 10.1 Addressing 10.2 32 Bit Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10.3 16 Bit Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10.4 Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10.4.1 Read Cycle 10.4.2 Write Cycle 11.0 Power-up and Initialization of the ZL50070 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 11.1 Device Reset and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 11.2 Power Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 11.3 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 12.0 IEEE 1149.1 Test Access Port 12.1 Test Access Port (TAP 12.2 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 12 ...

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... Group Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 14.5 Input Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 14.6 Output Clock Control Register 14.7 Block Init Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 14.8 Block Init Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 15.0 DC/AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 ZL50070 Table of Contents 4 Zarlink Semiconductor Inc. Data Sheet ...

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... Figure 1 - ZL50070 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure Channel Basic Switch Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 3 - ZL50070 Channel and Stream Provisioning Example at Multiple Rates . . . . . . . . . . . . . . 17 Figure 4 - Input and Output Data Rate Conversion Example Figure 5 - Input Sampling Point Delay Programming Figure 6 - Output Bit Advancement Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 7 - Data Throughput Delay for Constant Delay ...

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... Table 23 - BER Counter Group and Stream Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 24 - Group Control Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 25 - Group Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 26 - Input Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 27 - Output Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 28 - Block and Power-up Initialization Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ZL50070 List of Tables 6 Zarlink Semiconductor Inc. Data Sheet ...

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... Electrical Characteristics - CKo to Other CKo1 Skew“ 61 Figure 18 "CKo to other CKo Skew" ZL50070 Change Clarified WAIT signal description in Read Cycle. Corrected WAIT signal tristate timing in Read Cycle. Clarified WAIT signal description in Write Cycle. Corrected WAIT signal tristate timing in Write Cycle. ...

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... STiB SToC SToA FPo Y [9] [10] [11] [11] [12] [1] STiC STiC SToD STiD STiA SToB AA [10] [11] [11] [12] [13] [13] STiD STiA SToB CKo SToC STiC AB [11] [12] [12] [1] [13] [14] ZL50070 D[7] D[4] D[0] A[18] A[14] A[10] D[5] D[3] A[17] A[11] D[1] A[15] A[9] D[28] D[23] D[17] D[8] A[16] A[13] A[5] STiB D[24] D[18] D[14] D[2] A[12] A[4] [0] V D[29 D[10 DD_ DD_ DD_ DD_ DD_ CORE IO CORE IO CORE V ...

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... AA5, W9, AA9, U11, AA14, Y16, AB20, V17, AA21, W21, V22 E7, C3, G4, J5, K6, J1, M2, STiB0-23 P2, R5, V2, T5, Y3, W6, V8, Y8, AB9, AA11, AB15, V15, Y18, Y19, AB22, Y22, R20 ZL50070 Name TDM Interface Power Supply for the Core Logic: +1.8 V Power Supply for the I/O: +3.3 V DD_IO V Ground SS Serial TDM Input Data ’ ...

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... SToC0-23 R2, T3, V3, U5, Y4, U8, AB5, AB8, W11, V12, Y15, W16, AA20, U18, V20, T20, T22 ZL50070 Name Serial TDM Input Data ’C’ Streams (5 V Tolerant Input with Internal Pull-down) The data rate of these input streams can be selected in a group either 8.192 Mbps or 16.384 Mbps. The stream is unused when its input group rate is 65 ...

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... These optional TDM clock inputs are at 8.192 MHz, 16.384 MHz, 32.678 MHz or 65.536 MHz. The frequency of each clock input is automatically detected by the ZL50070. Refer to Section 2.0 for TDM timing options. The active clock edge may be either rising or falling, programmed by the Input Clock Control Register (Section 14 ...

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... F18, F19, F21, G18, H17, H18, H20, J18, J19, J22, K18, K20, K21, L17, L21, L22, M20, M21, N18, N20, P21, P22, AB13, AB14 ZL50070 Name ST-BUS/GCI-Bus Clock Outputs (3.3 V Outputs with Slew-Rate Control) These clock outputs can be programmed to generate 8.192 MHz, 16 ...

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... ZL50070. DS Data Strobe Input (5 V Tolerant Input) Active low input used with CS to enable read and write access to the ZL50070. R/W Read/Write Input (5 V Tolerant Input) This input controls the direction of the data bus lines (D31 - 0) during a microprocessor access. This pin is set high and low for the read and write access respectively ...

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... Device Reset (5 V Tolerant Schmitt-Triggered Input) Asynchronous reset input used to initialize the ZL50070 Reset 1 = Normal See Section 11.0, Power-up and Initialization of the ZL50070 for detailed description of Reset state. IEEE 1149.1 Test Access Port (TAP) TDi Test Data (5 V Tolerant Input with Internal Pull-up) Serial test data input ...

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... Switch Operation The ZL50070 switches 64 kbps and Nx64 kbps data and voice channels from the TDM input streams, to timeslots in the TDM output streams. The device is non-blocking; all 24 K input channels can be switched through to the outputs. Any input channel can be switched to any available output channel. ...

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... The ZL50070 is a large switch with a comprehensive list of user configurable, ’per-group’ programmable features. In order to facilitate ease of use, the ZL50070 offers a simple programming model. Streams are grouped in sets of four, with each group sharing the same configured characteristics. In this way it is possible to reduce programming complexity, while still maintaining flexible ‘ ...

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... Mbps or 8 Mbps, STiA23, STiB23, STiC23, STiD23 are all active An example of ZL50070 mixed rate provisioning is given in Figure . In this example, the output streams follow the same data rate as the input streams. The example shows that it is possible to have different groups operating at different data rates ...

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... Input Clock (CKi) and Input Frame Pulse (FPi) Timing The input timing for the ZL50070 can be set for one of four different frequencies. They can also be set for ST-BUS or GCI-Bus mode with positive or negative input. The CKi0 and FPi0 input timing must be provided in order for the device to be used ...

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... To be able to interface with external buffers, the output signals can be set to enter a high impedance or drive high state on a per-channel basis. The Per-Channel Function (bits 31 - 29) in the Connection Memory Bits can be set to 001 to drive the channel output high 000, 110 or 111 to set the channel into a high impedance state. ZL50070 CK_SEL0 Input CKi0 and FPi0 0 8 ...

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... Example: With a setting of 01111 the sampling point for bit 7 will be 3 1/2 bits Figure 5 - Input Sampling Point Delay Programming There are limitations when the ZL50070 is programmed to use CKi2 - 0 as the input stream clock source as opposed to the internal clock: • The granularity of the delay becomes 1/2 the selected reference clock period, or 1/4 bit, whichever is longer • ...

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... The OSBA bits in the Group Control Registers are used to set the bit-advancement for each of the corresponding serial output stream groups. Figure 6 illustrates the effect of the OSBA settings on the output timing. There are limitations when the ZL50070 is programmed to use CKi2 - 0 as the output stream clock source: • ...

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... Message Mode (010), the Connection Memory’s lowest data byte (bits output in the timeslot, in the outgoing timeslot. Refer to Section 14.1.1, Connection Memory Bit Functions, for programming details To increase programming bandwidth, the ZL50070 has separate addressable 32 bit memory locations, called Connection Memory Least Significant Bytes (LSB), which provide direct access to the Connection Memories’ ...

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... N-2 N-1 CH0 CH1 CH2 CH3 N-2 N-1 CH0 CH1 CH2 CH3 N-2 N-1 CH0 CH1 CH2 CH3 N-2 N-1 CH0 CH1 CH2 CH3 Figure 8 - Data Throughput Delay for Variable Delay ZL50070 N-2 N-1 CH0 CH1 CH2 CH3 N-2 N-1 CH0 CH1 CH2 CH3 N-2 N-1 CH0 CH1 CH2 CH3 N-2 N-1 CH0 CH1 CH2 CH3 CH4 CH5 CH6 ...

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... Bit Error Rate Tester The ZL50070 has one Bit Error Rate (BER) transmitter and one BER receiver for each pair of input and output streams, resulting in 96 transmitters connected to the output streams and 96 receivers associated with the input streams. Each transmitter can generate a BER sequence with a pattern of 2 O.151). Each transmitter can start at any location on the stream and will last for a minimum of 1 channel to a maximum of 1 frame time (125 µ ...

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... TDM output stream to destination TDM input stream. 10.0 Microprocessor Port The ZL50070 has a generic microprocessor port that provides access to the internal Data Memory (read access only), Connection Memory, and Control Registers. The port size can be configured to be either 32 bit or 16 bit, controlled by the D16B pin. ...

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... In Intel Bus Mode ( and SIZ1 - 0 form active low byte enable signals, consistent with BE3 - 0 available on the Intel i960 processor, as shown in Table 8. Table Bit Intel Mode Bus Enable Signals Byte addressing applies only to write accesses. On read cycles, all 32 bits are output on every access. ZL50070 Memory/Register Bits 40200 Bits 31:24 (MSB) ...

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... Bit Bus Operation In 16 bit mode (D16B = 1), D15 - 0 are used for data transfers to/from the ZL50070. D31 - 16 are unused and must be connected to a defined logic level. D15 on the bus maps to Bit 31 and Bit 15 of the internal 32 bit memory or register, D14 maps to Bit 30 and Bit 14, etc. ...

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... When the ZL50070 sees the CS signal go inactive high, it tri-states the data bus, D31 - 0 (D15 - bit Mode) and the DTA, BERR and the WAIT signals. However goes inactive high before DS goes inactive high, the DTA, BERR and WAIT signals are driven inactive high before they are tri-stated • ...

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... The microprocessor asserts the R/W control signal low, to signal a write cycle. It also drives the address A, data transfer size, SIZ1 - 0, and chip select logic drives the CS signal active low to select the ZL50070 • The microprocessor then drives the data bus, D31 - 0 (D15 - bit Mode) with the data to be written, and then drives the DS signal active low, to signal the start of the bus cycle ...

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... Power-up and Initialization of the ZL50070 11.1 Device Reset and Initialization The PWR pin is used to reset the ZL50070. When this pin is low, the following functions are performed: • Asynchronously puts the microprocessor port in a reset state • Tristates all of the output streams (SToA0 - 23, SToB0 - 23, SToC0 - 23 and SToD0 - 23) • ...

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... Register. 12.1 Test Access Port (TAP) The Test Access Port (TAP) accesses the ZL50070 test functions. The interface consists of 4 input and 1 output signal. as follows: • Test Clock (TCK) - TCK provides the clock for the test logic. The TCK does not interfere with any on-chip clock and thus remains independent in the functional mode ...

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... When JTAG is not in use, this pin must be tied low for normal operation. The TAP signals are only applied when the ZL50070 is required test mode. When in normal, non-test mode, TRST must be connected low to disable the test logic. The remaining test pins may be left unconnected. ...

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... Table 13 - Connection Memory Group Address Mapping ZL50070 Description Table 12 - Memory Map (continued) Address Range Output (Hex) Group 000000 - 000FFF 12 001000 - 001FFF 13 002000 - 002FFF 14 003000 - 003FFF 15 004000 - 004FFF 16 005000 - 005FFF 17 006000 - 006FFF ...

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... Table 15. It shows the maximum number of timeslots that a stream can have, but the actual number of timeslots available depends on the output data rates, as illustrated in Table 1 and Table 14. SToAn 126 127 Table 15 - Connection Memory Timeslot Address Offset Range ZL50070 Address Range Output (Hex) Group 00A000 - 00AFFF 22 00B000 - 00BFFF 23 Output Stream ...

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... ZL50070 Timeslot SToAn SToBn SToCn 128 128 129 129 - - 254 254 255 255 256 256 257 257 - - 510 510 511 511 512 513 - 1021 1022 1023 Table 15 - Connection Memory Timeslot Address Offset Range (continued) Zarlink Semiconductor Inc. Address Offset hex SToDn ...

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... V/D Voice/Data Control When this bit is low, the corresponding channel is for voice. When this bit is high, the corresponding channel is for data ICL1 - 0 Input Coding Law ICL1 - Table 16 - Connection Memory Bits (CMB) ZL50070 ICL OCL OCL ...

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... Memory LSB associated with channels particular stream, the data bus D31 - 24 carry data for channel 0, D23 - 16 carry data for channel 1, D15 - 8 carry data for channel 2, and carry data for channel 3. Addressing into each of the streams is illustrated in Table 17. ZL50070 H 26 ...

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... Within each stream group, the mapping of each of the actual output streams, SToAn, SToBn, SToCn and SToDn, depends on the output rate programmed into the Group Control Registers. The address offsets to these control areas for each of the output streams are illustrated in Table 18. ZL50070 Address Range Output ...

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... The address ranges for the data memory portion corresponding to each of the actual input streams, STiAn, STiBn, STiCn and STiDn, for any particular input group number is calculated by adding the Start Address for the particular group, as indicated in Table 19, to the appropriate Address Offset Range, as indicated in Table 20. The time-slots ZL50070 Address Range Input ...

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... D0 location. If the BCE bit is set, then the BER counter for the corresponding stream and timeslot is enabled for the duration of that timeslot. If the BCE bit is cleared the counter is disabled. Input Group Data Rate Time-slot Range 65 Mbps 32 Mbps 16 Mbps Table 22 - BER Enable Control Memory Stream Address Offset at Various Output Rates ZL50070 Address Range Input Address (Hex) Group 030000 - 0303FF 12 ...

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... BER Input Group BER Input Stream STiA23 STiB23 STiC23 STiD23 Table 23 - BER Counter Group and Stream Address Mapping ZL50070 Input Streams 0 - 127 STiAn STiBn STiCn STiDn Start Address (Hex) STiA0 40000 STiB0 40080 STiC0 40100 STiD0 ...

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... Group Control Registers The ZL50070 addresses the issues of a simple programming model and automatic stream configuration by defining a basic switching bit rate of 65.536 Mbps and by grouping the I/O streams. Each TDM I/O group contains 4 input and 4 output streams. The 4 input streams in the same group have identical input characteristics, and similarly, the 4 output streams in the same group have identical output characteristics ...

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... OSSRC1 - Unused Reserved. In normal functional mode, these bits MUST be set to zero. 9 ISI Input Stream Inversion For normal operation, this bit is set low. To invert the input stream, set this bit high. Table 25 - Group Control Register (continued) ZL50070 ...

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... Otherwise, the data rate cannot exceed the selected clock source’s rate ISSRC1 - 0 Input Stream Clock Source Select ISSRC1 - 0 Table 25 - Group Control Register (continued) The Group Control Register is a static control register. Changes to bit settings may disrupt data flow on the selected port for a maximum of 2 frames. ZL50070 ...

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... When this bit is high, FPi0 is set for active low. 0 CKIPOL0 Clock Polarity Selection for CKi0 When this bit is low, CKi0 is set for the positive clock edge. When this bit is high, CKi0 is set for the negative clock edge. ZL50070 ...

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... The output clock rate can not exceed the selected clock source rate. All rates are avail able when the internal system clock is selected as clock source. CKO3RATE1 - CKO3 Output Clock Source for CKo3 and FPo3 SRC CKO3SRC1 - Table 27 - Output Clock Control Register ZL50070 FPO CKO CKO3 CKO3 ...

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... SRC CKO2SRC1 - 0 13 GCO GCI-Bus Selection for FPo1 SEL1 When this bit is low, FPo1 is set for ST-BUS mode. When this bit is high, FPo1 is set for GCI-Bus mode. Table 27 - Output Clock Control Register (continued) ZL50070 FPO CKO CKO3 ...

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... When this bit is high, FPo0 is set for GCI-Bus mode. 5 FPO Frame Pulse Polarity Selection for FPo0 POL0 When this bit is low, FPo0 is set for active high. When this bit is high, FPo0 is set for active low. Table 27 - Output Clock Control Register (continued) ZL50070 FPO ...

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... However possible to perform a block initialization at any time. During Block Initialization, the value of the Block Init Register is copied to all connection memory locations in an operation that runs in about 120 µs. If the Block Init Register is modified during a block initialization, the new value used is ignored. ZL50070 ...

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... Table 28 - Block and Power-up Initialization Status Bits Any access to the connection memory or the data memory during a block initialization or a reset initialization will result in a bus error, BERR. All TDM outputs are tri-stated during any block initialization. ZL50070 Description 0 if Block initialization is completed; ...

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... Voltages are with respect to ground (VSS) unless otherwise stated. Characteristics 2 1 Core Supply Current 2 I/O Supply Current 3 Leakage Current 4 Dynamic Power Dissipation 5 Input High Voltage 6 Input Low Voltage 3 7 Input Leakage-input pins 8 Input Leakage-bidirectional pins 9 Pull-up Current ZL50070 ) unless otherwise stated SS Sym. Min. V -0.5 DD_IO V -0.5 DD_CORE V -0.5 I_3V V -0.5 I_5V ...

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... Characteristics are over recommended operating conditions unless otherwise stated Electrical Characteristics - FPi0-2 and CKi0-2 Timing No. Characteristic (Figure ) 1 FPi0-2 Input Frame Pulse Setup Time 2 FPi0-2 Input Frame Pulse Hold Time 3 FPi0-2 Input Frame Pulse width ZL50070 1 Sym. Min. Typ. Max 2.4 ...

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... When using input clock source CKi2-0 instead of the internal APLL clock source. Note 5: When using internal APLL clock source and the CKi0 frequency is higher than or equal to twice the data rate. FPi t CKi Input Frame Boundary Figure 12 - Frame Pulse Input and Clock Input ZL50070 2 Sym. Min. Typ 15.26 ...

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... Note 1: Characteristics are over recommended operating conditions unless otherwise stated. Note 2: Typical figures are at 25°C, V DD_CORE subject to production testing. FPi0 CKi0 FPi1, 2 CKi1, 2 Frame Boundary ZL50070 2 Sym. Min. Typ. Max. t -30 +30 CKSK at 1.8 V and V at 3.3 V and are for design aid only: not guaranteed and not ...

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... DD_CORE subject to production testing. Note 3: CKo clock source set to internal 131 MHz APLL, and CKi0 and FPi0 meet all the timing requirements. Note 4: When CKo source is set to one of the CKi/FPi, its output timings directly follow its source. ZL50070 2 Sym. Min. Typ ...

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... Jitter at CKO0-3 (32.768 MHz) 4 Jitter at CKO0-3 (65.536 MHz) Note 1: CKi at 8 MHz, output clock source set to internal APLL. No jitter presented on the Cki0 input. Note 2: For 65.536 MHz output clock, the total loading on the output should not be larger than 10pF. ZL50070 t FPOH t CKOP t FPOH ...

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... All of these specifications refer to ST-BUS inputs and outputs with clock source set to CKi. Note 3: Typical figures are at 25°C, V DD_CORE subject to production testing. Note 4: Loads on all serial outputs set to 30 pF. Note 5: High Impedance is measured by pulling to the appropriate rail with ZL50070 2 to CKi 3 Sym. Min. Typ. Max. t 3.5 CKDP 4 ...

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... Note 1: CKi frequency is assumed to be twice of the STin data rate, so that the sampling point is at the 3/4 point of the bit cell 1/2 clock period after the active clock edge Note 2: If CKi frequency is the same as the STin data rate, the sampling point moves to the 1/2 point of the bit cell, or 1/2 clock period after the active clock edge. ZL50070 t CKDN t ...

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... Data Capture points vary with respect to CKo edge depending on clock rates & fractional delay settings. Note 2: All of these specifications refer to ST-BUS inputs, ST-BUS outputs and CKo outputs set to internal clock source. Note 3: Typical figures are at 25°C, V DD_CORE subject to production testing. Note 4: Loads on all serial outputs set to 30 pF. ZL50070 CKo Sym. Min. Typ. t 7.3 ...

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... Note 1 : CKo frequency is assumed to be twice of the STin data rate, so that the sampling point is at the 3/4 point of the bit cell 1/2 clock period after the active clock edge Note 2: If CKo frequency is the same as the STin data rate, the sampling point moves to the 1/2 point of the bit cell, or 1/2 clock period after the active clock edge. ZL50070 t SONV t ...

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... All of these specifications refer to ST-BUS inputs, ST-BUS outputs and CKo outputs set to internal clock source. Note 2: Typical figures are at 25°C, V DD_CORE subject to production testing. CKo0 CKo3 t CKOS1-0 CKo1 t CKOS2-0 CKo2 t CKOS2-3 ZL50070 1 Skew Sym. Min CKOS1 CKOS2 CKOS1-3 t ...

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... CS deasserted to WAIT tri-stated UDS/LDS skew UDS/LDS to DS set-up Note 1: Typical figures are at 25°C, V DD_CORE subject to production testing. Note 2: High Impedance is measured by pulling to the appropriate rail with ZL50070 Sym. Min. Typ DSRE t 0 CSRE t 0 CSS t 0 ...

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... DS t CSRE CS A18-A0 RWN,SIZ D31-D0 READ D31-D0 WRITE Hi-Z DTA BERR Hi-Z WAIT Figure 19 - Microprocessor Bus Interface Timing DS SIZ1-SIZ0 (BE1-BE0 or UDS, LDS) Figure 20 - Intel Mode Timing ZL50070 t DSRE t CSS t ADS VALID VALID READ DATA t WDS VALID WRITE DATA t DSR t AKD t CSWA t WDD t DSRE ...

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... Characteristics are over recommended operating conditions unless otherwise stated. Note 2: Typical figures are at 25°C, V DD_CORE subject to production testing. TCK t TMSS TMS t TDIS TDi TDo TRST PWR Figure 21 - IEEE 1149.1 Test Port & PWR Reset Timing ZL50070 Sym. Min. Typ. t 100 TCKP t TCKF t 20 TCKH t 20 TCKL t ...

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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...