zl50407 Zarlink Semiconductor, zl50407 Datasheet - Page 43

• Manufacturer Part Number: zl50407
• Description: Lightly Managed/unmanaged 8-port 10/100m + 1-port 10/100/1000m Ethernet Switch
• Manufacturer: Zarlink Semiconductor

10.0
10.1
The RMAC ethernet port can function in GPSI (7WS) mode. In this mode, the TXD[0], RXD[0] serve as TX data, RX
data and respectively. The link and duplex of the port can be controlled by programming the ECR register. Only
port-based VLAN is supported with GPSI interface.
11.0
11.1
11.1.1
SCLK is the primary clock for the ZL50407 device. The speed requirement is based on the system configuration.
Below is a table for a few configuration.
11.1.2
M_CLK is a 50 MHz clock used for the RMAC ports (ports 0-7).
If none of the RMAC ports are configured in RMII mode or Reverse MII mode, a different clock frequency can be
applied to M_CLK, as long as it's less than 50 MHz. In this case, register USD must be set to provide an internal
1usec timing.
11.1.3
GREF_CLK is a 125 MHz reference clock required for the GMAC port (port 9).
If the device is in a 9 port 10/100 configuration only, GREF_CLK can be a lower frequency clock and can be
connected to M_CLK to reduce the number of clock sources.
If port 9 is not being used, GREF_CLK can be left unconnected.
11.1.4
TCK is a clock used for the JTAG port. The frequency on this clock can vary. Refer to “JTAG (IEEE 1149.1-2001)”
on page 122 for the frequency range.
11.2
11.2.1
MDC is used for the MII Management Interface and clocks data on MDIO. It is generated by the device from
M_CLK and is equal to 500 kHz (M_CLK/100). If a different speed clock other than 50MHz is used on M_CLK, the
USD register must be programmed to reset MDC.
8 Port 10/100M + 1 port 1000M
6-9 ports 10/100M
1-5 ports 10/100M
Clock Requirements
Clock Generation
GPSI connection
Clocks
GPSI (7WS) Interface
System Clock (SCLK) speed requirement
RMAC Reference Clock (M_CLK) speed requirement
GMAC Reference Clock (GREF_CLK) speed requirement
JTAG Test Clock (TCK) speed requirements
MDC
Configuration
Table 11 - SCLK Speed Requirements
Zarlink Semiconductor Inc.
ZL50407
43
50 MHz
25 Mhz
100 MHz
Minimum SCLK speed
required
Data Sheet