89hpes24t3g2 Integrated Device Technology, 89hpes24t3g2 Datasheet - Page 7

• Manufacturer Part Number: 89hpes24t3g2
• Description: 24-lane, 3-port Gen2 Pcie I/o Expansion Switch
• Manufacturer: Integrated Device Technology

IDT 89HPES24T3G2 Data Sheet
JTAG_TRST_N
REFRES0,
REFRES2,
REFRES4,
V
REFRES1
REFRES3
REFRES5
V
V
Signal
Signal
V
DD
V
DD
DD
DD
DD
V
CORE
PEHA
PETA
SS
PEA
I/O
Type
Type
Table 7 Power, Ground, and SerDes Resistor Pins
I/O
I/O
I/O
I
I
I
I
I
I
I
JTAG Reset. This active low signal asynchronously resets the boundary
scan logic and JTAG TAP Controller. An external pull-up on the board is
recommended to meet the JTAG specification in cases where the tester
can access this signal. However, for systems running in functional mode,
one of the following should occur:
Port 0 External Reference Resistors. Provides a reference for the Port 0
SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-
tor should be connected from these pins to ground.
Port 2 External Reference Resistors. Provides a reference for the Port 2
SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-
tor should be connected from these pins to ground.
Port 4 External Reference Resistors. Provides a reference for the Port 4
SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-
tor should be connected from these pins to ground.
Core V
I/O V
PCI Express Analog Power. Serdes analog power supply (1.0V).
PCI Express Analog High Power. Serdes analog power supply (2.5V).
PCI Express Transmitter Analog Voltage. Serdes transmitter analog
power supply (1.0V).
Ground.
Table 6 Test Pins (Part 2 of 2)
1) actively drive this signal low with control logic
2) statically drive this signal low with an external pull-down on the board
DD.
DD.
LVTTL I/O buffer power supply.
Power supply for core logic.
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Name/Description
Name/Description
May 7, 2008