89hpes24n3a Integrated Device Technology, 89hpes24n3a Datasheet

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89hpes24n3a

Manufacturer Part Number
89hpes24n3a
Description
24-lane, 3-port Pcie I/o Expansion Switch
Manufacturer
Integrated Device Technology
Datasheet

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Device Overview
PCI Express® switching solutions. The PES24N3A is a 24-lane, 3-port
peripheral chip that performs PCI Express packet switching with a
feature set optimized for high performance applications such as servers,
storage, and communications/networking. It provides connectivity and
switching functions between a PCI Express upstream port and two
downstream ports and supports switching between downstream ports.
Features
Block Diagram
© 2008 Integrated Device Technology, Inc.
The 89HPES24N3A is a member of the IDT PRECISE™ family of
– Twenty-four 2.5 Gbps PCI Express lanes
– Three switch ports
– Upstream port configurable up to x8
– Downstream ports configurable up to x8
– Low-latency cut-through switch architecture
– Support for Max Payload Size up to 2048 bytes
– One virtual channel
– Eight traffic classes
– PCI Express Base Specification Revision 1.1 compliant
High Performance PCI Express Switch
SerDes
Logical
Layer
Phy
Multiplexer / Demultiplexer
Transaction Layer
Data Link Layer
SerDes
Logical
Layer
Phy
Frame Buffer
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
...
®
x8 Upstream Port and Two x8 Downstream Ports
SerDes
Logical
Layer
Phy
24-Lane 3-Port
PCI Express® Switch
Route Table
Figure 1 Internal Block Diagram
SerDes
Logical
Layer
24 PCI Express Lanes
Phy
Multiplexer / Demultiplexer
3-Port Switch Core
Transaction Layer
Data Link Layer
SerDes
Logical
Layer
Phy
1 of 31
...
– Automatic per port link width negotiation to x8, x4, x2 or x1
– Automatic lane reversal on all ports
– Automatic polarity inversion on all lanes
– Ability to load device configuration from serial EEPROM
– PCI compatible INTx emulation
– Bus locking
– Requires no external components
– Incorporates on-chip internal memory for packet buffering and
– Integrates twenty-four 2.5 Gbps embedded SerDes with 8B/
– Supports ECRC and Advanced Error Reporting
– Internal end-to-end parity protection on all TLPs ensures data
– Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O
– Compatible with Hot-Plug I/O expanders used on PC and
Arbitration
Flexible Architecture with Numerous Configuration Options
Legacy Support
Highly Integrated Solution
Reliability, Availability, and Serviceability (RAS) Features
SerDes
Logical
Layer
Port
Phy
queueing
10B encoder/decoder (no separate transceivers needed)
integrity even in systems that do not implement end-to-end
CRC (ECRC)
server motherboards
SerDes
Logical
Layer
Phy
Multiplexer / Demultiplexer
Scheduler
Transaction Layer
Data Link Layer
SerDes
Logical
Layer
Phy
...
89HPES24N3A
SerDes
Data Sheet
Logical
Layer
Phy
April 23, 2008
DSC 6921

Related parts for 89hpes24n3a

89hpes24n3a Summary of contents

Page 1

... Device Overview The 89HPES24N3A is a member of the IDT PRECISE™ family of PCI Express® switching solutions. The PES24N3A is a 24-lane, 3-port peripheral chip that performs PCI Express packet switching with a feature set optimized for high performance applications such as servers, storage, and communications/networking. It provides connectivity and switching functions between a PCI Express upstream port and two downstream ports and supports switching between downstream ports ...

Page 2

... IDT 89HPES24N3A Data Sheet ◆ Power Management – Utilizes advanced low-power design techniques to achieve low typical power consumption – Supports PCI Power Management Interface specification (PCI-PM 1.1) • Supports device power management states: D0 cold – Unused SerDes are disabled ◆ Testability and Debug Features – ...

Page 3

... IDT 89HPES24N3A Data Sheet Processor SMBus PES24N3A SSMBCLK SSMBDAT MSMBCLK MSMBDAT (a) Unified Configuration and Management Bus Hot-Plug Interface The PES24N3A supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the PES24N3A utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset and configura- tion, whenever the state of a Hot-Plug output needs to be modified, the PES24N3A generates an SMBus transaction to the I/O expander with the new value of all of the outputs ...

Page 4

... IDT 89HPES24N3A Data Sheet Pin Description The following tables list the functions of the pins provided on the PES24N3A. Some of the functions listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level ...

Page 5

... IDT 89HPES24N3A Data Sheet Signal GPIO[0] GPIO[1] GPIO[2] GPIO[3] GPIO[4] GPIO[5] GPIO[6] GPIO[7] Signal CCLKDS CCLKUS MSMBSMODE Type Name/Description I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P2RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 2 I/O General Purpose I/O ...

Page 6

... IDT 89HPES24N3A Data Sheet Signal PERSTN RSTHALT SWMODE[3:0] Signal JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N Signal V CORE Type Name/Description I Fundamental Reset. Assertion of this signal resets all logic inside PES24N3A and initiates a PCI Express fundamental reset. I Reset Halt. When this signal is asserted during a PCI Express fundamental reset, PES24N3A executes the reset procedure and remains in a reset state with the Master and Slave SMBuses active ...

Page 7

... IDT 89HPES24N3A Data Sheet Signal V APE Pin Characteristics Note: Some input pads of the PES24N3A do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left floating can cause a slight increase in power consumption ...

Page 8

... IDT 89HPES24N3A Data Sheet Function System Pins CCLKDS CCLKUS MSMBSMODE PERSTN RSTHALT SWMODE[3:0] EJTAG / JTAG JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N 1. Internal resistor values under typical operating conditions are 54K Ω for pull-up and 251K Ω for pull-down. 2. Schmitt Trigger Input (STI). ...

Page 9

... IDT 89HPES24N3A Data Sheet Logic Diagram — PES24N3A PEREFCLKP Reference PEREFCLKN Clocks REFCLKM PE0RP[0] PCI Express PE0RN[0] Switch SerDes Input PE0RP[7] Port 0 PE0RN[7] PE2RP[0] PCI Express PE2RN[0] Switch SerDes Input PE2RP[7] Port 2 PE2RN[7] PE4RP[0] PCI Express PE4RN[0] Switch SerDes Input PE4RP[7] ...

Page 10

... IDT 89HPES24N3A Data Sheet System Clock Parameters Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 13 and 14. Parameter Refclk Input reference clock frequency range FREQ 2 Refclk Duty cycle of input clock Rise/Fall time of input clocks Differential input voltage swing ...

Page 11

... IDT 89HPES24N3A Data Sheet Parameter T Max time between jitter median & max deviation RX-EYE-MEDIUM TO MAX JITTER T Unexpected Idle Enter Detect Threshold Integration Time RX-IDLE-DET-DIFF- ENTER TIME T Lane to lane input skew RX-SKEW 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.1 ...

Page 12

... IDT 89HPES24N3A Data Sheet JTAG_TCK JTAG_TDI JTAG_TMS JTAG_TDO JTAG_TRST_N Recommended Operating Supply Voltages Symbol V CORE Internal logic supply DD V I/O I/O supply except for SerDes LVPECL/CML PCI Express Digital Power DD V APE PCI Express Analog Power PCI Express Serial Data Transmit ...

Page 13

... IDT 89HPES24N3A Data Sheet Recommended Operating Temperature Power Consumption Typical power is measured under the following conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages defined in Table 13 (and also listed below). Maximum power is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximum voltages defined in Table 13 (and also listed below) ...

Page 14

... IDT 89HPES24N3A Data Sheet Heat Sink Table 17 lists heat sink requirements for the PES24N3A under three common usage scenarios. As shown in this table, a heat sink is not required in most cases. . Air Flow Zero 3.9”x6.2” (ExpressModule form factor) or larger Zero 1 m/S or more Table 17 Heat Sink Requirements Based on Air Flow and Board Characteristics Thermal Usage Examples The junction-to-ambient thermal resistance is a measure of a device’ ...

Page 15

... IDT 89HPES24N3A Data Sheet DC Electrical Characteristics Values based on systems running at recommended supply voltages, as shown in Table 13. Note: See Table 8, Pin Characteristics, for a complete I/O listing. I/O Type Parameter Serial Link PCIe Transmit V Differential peak-to-peak output voltage TX-DIFFp-p V De-emphasized differential output voltage TX-DE-RATIO V DC Common mode voltage ...

Page 16

... IDT 89HPES24N3A Data Sheet I/O Type Parameter Other I/Os LOW Drive I OL Output I OH High Drive I OL Output I OH Schmitt Trig ger Input V IH (STI) Input Capacitance C IN Leakage Inputs I/O / LEAK W O Pull-ups/downs I/O LEAK WITH Pull-ups/downs 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.1. ...

Page 17

... IDT 89HPES24N3A Data Sheet Package Pinout — 420-BGA Signal Pinout for PES24N3A The following table lists the pin numbers and signal names for the PES24N3A device. Pin Function Alt Pin B10 B11 SS A4 JTAG_TDI B12 A5 JTAG_TMS B13 ...

Page 18

... IDT 89HPES24N3A Data Sheet Pin Function Alt Pin F23 F24 V APE K5 DD F25 V CORE K22 DD F26 V CORE K23 DD G1 PE2TN07 K24 G2 PE2TP07 K25 K26 DD G4 PE2RN07 L1 G5 PE2RP07 L2 G22 PE4RP00 L3 G23 PE4RN00 L4 G24 G25 PE4TP00 L22 G26 ...

Page 19

... IDT 89HPES24N3A Data Sheet Pin Function Alt Pin AA5 PE2RP00 AC3 AA22 PE4RP07 AC4 AA23 PE4RN07 AC5 AA24 V PE AC6 DD AA25 PE4TP07 AC7 AA26 PE4TN07 AC8 AB1 V AC9 SS AB2 V AC10 SS AB3 V CORE AC11 DD AB4 V CORE AC12 DD AB5 V CORE AC13 DD AB6 V AC14 ...

Page 20

... IDT 89HPES24N3A Data Sheet Power Pins V Core V Core C14 F25 C16 F26 M26 D8 P1 D10 P26 D12 T1 D13 T26 D15 V1 D17 V26 D18 AB3 D19 AB4 D21 AB5 D22 AB23 E6 AB24 E7 AC3 E9 AC4 E11 AC5 E13 AC23 E15 ...

Page 21

... IDT 89HPES24N3A Data Sheet Ground Pins A23 A24 A25 A26 B1 B2 B25 B26 C10 C12 C18 C20 C22 C24 C25 F22 D11 F23 D14 H1 D16 H2 D20 H5 D23 H22 D24 H25 D25 H26 E1 K1 ...

Page 22

... IDT 89HPES24N3A Data Sheet Alternate Signal Functions Signals Listed Alphabetically Signal Name CCLKDS CCLKUS GPIO_00 GPIO_01 GPIO_02 GPIO_03 GPIO_04 GPIO_05 GPIO_06 GPIO_07 JTAG_TCK JTAG_TDI JTAG_TMS JTAG-TDO JTAG-TRST_N MSMBADDR_1 MSMBADDR_2 MSMBADDR_3 MSMBADDR_4 MSMBCLK MSMBDAT MSMBSMODE Pin GPIO Alternate B18 GPIO_00 A19 GPIO_01 ...

Page 23

... IDT 89HPES24N3A Data Sheet Signal Name PE0RN00 PE0RN01 PE0RN02 PE0RN03 PE0RN04 PE0RN05 PE0RN06 PE0RN07 PE0RP00 PE0RP01 PE0RP02 PE0RP03 PE0RP04 PE0RP05 PE0RP06 PE0RP07 PE0TN00 PE0TN01 PE0TN02 PE0TN03 PE0TN04 PE0TN05 PE0TN06 PE0TN07 PE0TP00 PE0TP01 PE0TP02 PE0TP03 PE0TP04 PE0TP05 PE0TP06 PE0TP07 I/O Type Location ...

Page 24

... IDT 89HPES24N3A Data Sheet Signal Name PE2RN00 PE2RN01 PE2RN02 PE2RN03 PE2RN04 PE2RN05 PE2RN06 PE2RN07 PE2RP00 PE2RP01 PE2RP02 PE2RP03 PE2RP04 PE2RP05 PE2RP06 PE2RP07 PE2TN00 PE2TN01 PE2TN02 PE2TN03 PE2TN04 PE2TN05 PE2TN06 PE2TN07 PE2TP00 PE2TP01 PE2TP02 PE2TP03 PE2TP04 PE2TP05 PE2TP06 PE2TP07 PE4RN00 PE4RN01 PE4RN02 ...

Page 25

... IDT 89HPES24N3A Data Sheet Signal Name PE4RN04 PE4RN05 PE4RN06 PE4RN07 PE4RP00 PE4RP01 PE4RP02 PE4RP03 PE4RP04 PE4RP05 PE4RP06 PE4RP07 PE4TN00 PE4TN01 PE4TN02 PE4TN03 PE4TN04 PE4TN05 PE4TN06 PE4TN07 PE4TP00 PE4TP01 PE4TP02 PE4TP03 PE4TP04 PE4TP05 PE4TP06 PE4TP07 PEREFCLKN1 PEREFCLKN2 PEREFCLKP1 PEREFCLKP2 PERSTN REFCLKM RSTHALT ...

Page 26

... IDT 89HPES24N3A Data Sheet Signal Name SSMBADDR_1 SSMBADDR_2 SSMBADDR_3 SSMBADDR_5 SSMBCLK SSMBDAT SWMODE_0 SWMODE_1 SWMODE_2 SWMODE_3 V CORE APE I/O Type Location B10 I A10 I B11 I/O A11 I/O B12 I B14 I A15 I B15 I A16 See Table 20 for a listing of power pins. ...

Page 27

... IDT 89HPES24N3A Data Sheet PES24N3A Pinout — Top View Core (Power I/O (Power (Power) Vss (Ground (Power) ...

Page 28

... IDT 89HPES24N3A Data Sheet PES24N3A Package Drawing — 420-Pin BX420/BXG420 April 23, 2008 ...

Page 29

... IDT 89HPES24N3A Data Sheet PES24N3A Package Drawing — Page Two April 23, 2008 ...

Page 30

... IDT 89HPES24N3A Data Sheet Revision History February 8, 2007: Initial publication. April 4, 2007: In Table 3, revised description for MSMBCLK signal. May 30, 2007: Added ZG device revision to Ordering Information. November 14, 2007: Added new parameter, Termination Resistor, to Table 9, Input Clock Requirements. March 25, 2008: Added and θ ...

Page 31

... IDT 89HPES24N3A Data Sheet Ordering Information A AAA NN Product Operating Device Family Family Voltage Valid Combinations 89HPES24N3AZCBX 420-pin BX420 package, Commercial Temperature 89HPES24N3AZGBX 420-pin BX420 package, Commercial Temperature 89HPES24N3A1ZCBX 420-pin BX420 package, Commercial Temperature 89HPES24N3AZCBXG 420-pin Green BX420 package, Commercial Temperature 89HPES24N3AZGBXG ...

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