89hpes12n3 Integrated Device Technology, 89hpes12n3 Datasheet - Page 5

• Manufacturer Part Number: 89hpes12n3
• Description: 12-lane, 3-port Pcie I/o Expansion Switch
• Manufacturer: Integrated Device Technology

IDT 89HPES12N3 Data Sheet
MSMBSMODE
SWMODE[3:0]
JTAG_TCK
JTAG_TDI
RSTHALT
TSTRSVD
Signal
CCLKDS
CCLKUS
PERSTN
Signal
Type
Type
I
I
I
I
I
I
I
I
I
Common Clock Downstream. The assertion of this pin indicates that all
downstream ports are using the same clock source as that provided to
downstream devices.This bit is used as the initial value of the Slot Clock
Configuration bit in all of the Link Status Registers for downstream ports.
The value may be override by modifying the SCLK bit in the PB_PCIELSTS
or PC_PCIELSTS register.
Common Clock Upstream. The assertion of this pin indicates that the
upstream port is using the same clock source as the upstream device. This
bit is used as the initial value of the Slot Clock Configuration bit in the Link
Status Register for the upstream port. The value may be overridden by
modifying the SCLK bit in the PA_PCIELSTS register.
Master SMBus Slow Mode. The assertion of this pin indicates that the
master SMBus should operate at 100 KHz instead of 400 KHz. This value
may not be overridden.
Fundamental Reset. Assertion of this signal resets all logic inside the
PES12N3 and initiates a PCI Express fundamental reset.
Reset Halt. When this signal is asserted during a PCI Express fundamental
reset, the PES12N3 executes the reset procedure and remains in a reset
state with the Master and Slave SMBuses active. This allows software to
read and write registers internal to the device before normal device opera-
tion begins. The device exits the reset state when the RSTHALT bit is
cleared in the PA_SWCTL register by an SMBus master.
Reserved. Reserved for future test mode. Must be tied to ground.
Switch Mode. These configuration pins determine the PES12N3 switch
operating mode.
0x0 - Transparent mode
0x1 -Transparent mode with serial EEPROM initialization
0x2 through 0x7 - Reserved
0x8 - 10-bit loopback test mode
0x9 - Reserved
0xA - Internal pseudo random bit stream self-test test mode
0xB - External pseudo random bit stream self-test test mode
0xC - Reserved
0xD - SerDes broadcast test mode
0xE - 0xF Reserved
JTAG Clock. This is an input test clock used to clock the shifting of data
into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is
independent of the system clock with a nominal 50% duty cycle.
JTAG Data Input. This is the serial data input to the boundary scan logic or
JTAG Controller.
Table 5 Test Pins (Part 1 of 2)
Table 4 System Pins
5 of 28
Name/Description
Name/Description
July 18, 2006