89hpes12t3g2 Integrated Device Technology, 89hpes12t3g2 Datasheet
89hpes12t3g2
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89hpes12t3g2 Summary of contents
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... Device Overview The 89HPES12T3G2 is a member of IDT’s PRECISE™ family of PCI Express® switching solutions. The PES12T3G2 is a 12-lane, 3-port Gen2 peripheral chip that performs PCI Express Base switching with a feature set optimized for high performance applications such as servers, storage, and communications/networking ...
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... IDT 89HPES12T3G2 Data Sheet – Unused SerDes are disabled. – Supports Advanced Configuration and Power Interface Spec- ification, Revision 2.0 (ACPI) supporting active link state ◆ Testability and Debug Features – Built in Pseudo-Random Bit Stream (PRBS) generator – Numerous SerDes test modes – ...
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... IDT 89HPES12T3G2 Data Sheet Processor SMBus PES12T3G2 SSMBCLK SSMBDAT MSMBCLK MSMBDAT (a) Unified Configuration and Management Bus Hot-Plug Interface The PES12T3G2 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the PES12T3G2 utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset and configura- tion, whenever the state of a Hot-Plug output needs to be modified, the PES12T3G2 generates an SMBus transaction to the I/O expander with the new value of all of the outputs ...
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... IDT 89HPES12T3G2 Data Sheet Pin Description The following tables list the functions of the pins provided on the PES12T3G2. Some of the functions listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level ...
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... IDT 89HPES12T3G2 Data Sheet Signal GPIO[0] GPIO[1] GPIO[2] GPIO[3] GPIO[4] GPIO[5] GPIO[6] GPIO[7] GPIO[11] Type Name/Description I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P2RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 2. ...
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... IDT 89HPES12T3G2 Data Sheet Signal CCLKDS CCLKUS MSMBSMODE PERSTN RSTHALT SWMODE[2:0] Signal JTAG_TCK JTAG_TDI Type Name/Description I Common Clock Downstream. The assertion of this pin indicates that all downstream ports are using the same clock source as that provided to downstream devices.This bit is used as the initial value of the Slot Clock Configuration bit in all of the Link Status Registers for downstream ports ...
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... IDT 89HPES12T3G2 Data Sheet Signal JTAG_TDO JTAG_TMS JTAG_TRST_N Signal REFRES0 REFRES2 REFRES4 V CORE PEA DD V PEHA DD V PETA Type Name/Description O JTAG Data Output. This is the serial data shifted out from the boundary scan logic or JTAG Controller. When no data is being shifted out, this signal is tri-stated ...
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... IDT 89HPES12T3G2 Data Sheet Pin Characteristics Note: Some input pads of the PES12T3G2 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left floating can cause a slight increase in power consumption ...
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... IDT 89HPES12T3G2 Data Sheet Function SerDes Reference REFRES0 Resistors REFRES2 REFRES4 1. Internal resistor values under typical operating conditions are 92K Ω for pull-up and 90K Ω for pull-down. 2. Schmitt Trigger Input (STI). Pin Name Type Buffer I/O Analog I/O I/O Table 8 Pin Characteristics (Part ...
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... IDT 89HPES12T3G2 Data Sheet Logic Diagram — PES12T3G2 Reference Clocks Reference Clock Frequency Selection PCI Express Switch SerDes Input Port 0 PCI Express Switch SerDes Input Port 2 PCI Express Switch SerDes Input Port 4 Master SMBus Interface Slave SMBus Interface System Pins PEREFCLKP[0] ...
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... IDT 89HPES12T3G2 Data Sheet System Clock Parameters Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 13 and 14. Parameter Description Refclk Input reference clock frequency range FREQ T Rising edge rate C-RISE T Falling edge rate C-FALL V Differential input high voltage ...
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... IDT 89HPES12T3G2 Data Sheet Parameter T Maximum time to transition to a valid Idle after sending TX-IDLE-SET-TO- an Idle ordered set IDLE T Maximum time to transition from valid idle to diff data TX-IDLE-TO-DIFF- DATA T Transmitter data skew between any 2 lanes TX-SKEW T Minimum Instantaneous Lone Pulse Width ...
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... IDT 89HPES12T3G2 Data Sheet Signal JTAG JTAG_TCK 1 JTAG_TMS , JTAG_TDI JTAG_TDO JTAG_TRST_N 1. The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N changes from Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high rising edge of JTAG_TCK when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state ...
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... IDT 89HPES12T3G2 Data Sheet Recommended Operating Supply Voltages Symbol V CORE Internal logic supply DD V I/O I/O supply except for SerDes LVPECL/CML PEA PCI Express Analog Power PEHA PCI Express Analog High Power DD V PETA PCI Express Transmitter Analog Voltage DD V Common ground SS 1 ...
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... IDT 89HPES12T3G2 Data Sheet Power Consumption Typical power is measured under the following conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages defined in Table 13 (and also listed below). Maximum power is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximum voltages defined in Table 13 (and also listed below) ...
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... IDT 89HPES12T3G2 Data Sheet DC Electrical Characteristics Values based on systems running at recommended supply voltages, as shown in Table 13. Note: See Table 8, Pin Characteristics, for a complete I/O listing. I/O Type Parameter Description Serial Link PCIe Transmit V Differential peak-to-peak output TX-DIFFp-p 2 voltage V Low-Drive Differential Peak to TX-DIFFp-p-LOW ...
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... IDT 89HPES12T3G2 Data Sheet I/O Type Parameter Description Serial Link PCIe Receive (cont.) V Differential input voltage (peak- RX-DIFFp-p to-peak) RL Receiver Differential Return RX-DIFF Loss RL Receiver Common Mode Return RX-CM Loss Z Differential input impedance RX-DIFF-DC (DC common mode impedance RX--DC Z Powered down input common RX-COMM-DC ...
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... IDT 89HPES12T3G2 Data Sheet I/O Type Parameter Description Capacitance C IN Leakage Inputs I/O / LEAK W O Pull-ups/downs I/O LEAK WITH Pull-ups/downs 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 2.0. 2. Depending upon conditions, values may fall outside the range specified with the default settings. Register settings are available to optimize values as needed. ...
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... IDT 89HPES12T3G2 Data Sheet Package Pinout — 324-BGA Signal Pinout for PES12T3G2 The following table lists the pin numbers and signal names for the PES12T3G2 device. Pin Function Alt Pin A1 V B17 B18 SS A3 PE0RN00 C1 A4 PE0RP00 ...
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... IDT 89HPES12T3G2 Data Sheet Pin Function Alt Pin H11 V CORE K13 DD H12 V K14 SS H13 V K15 SS H14 V PEHA K16 DD H15 V CORE K17 DD H16 PE4TN01 K18 H17 H18 PE4RN01 L2 J1 PE2RP02 PETA PE2TP02 L5 J4 REFRES2 CORE ...
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... IDT 89HPES12T3G2 Data Sheet Pin Function Alt Pin U1 V U10 U11 SS U3 SSMBCLK U12 U4 SSMBADDR_3 U13 U5 V U14 SS U6 MSMBCLK U15 U7 MSMBADDR_1 U16 U8 V PEA U17 U18 SS Alternate Signal Functions No Connection Pins Function Alt Pin V PETA ...
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... IDT 89HPES12T3G2 Data Sheet Power Pins V Core DD B14 D8 D9 D12 E5 E10 E13 F4 F7 F12 F14 H11 H15 J5 J9 J12 V Core V I K10 E6 B10 K14 E12 B16 L4 E14 C7 L12 F5 D11 M7 F15 M9 G6 F17 M11 G13 G2 M14 M6 J16 N5 M13 J17 ...
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... IDT 89HPES12T3G2 Data Sheet Ground Pins A11 A14 B12 B13 B15 C4 C9 C15 D1 D7 D13 E17 H10 L6 F6 H12 L7 F8 H13 L8 F9 H17 L9 F10 J6 L10 F11 J7 L11 F13 J8 L13 F16 J10 ...
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... IDT 89HPES12T3G2 Data Sheet Signals Listed Alphabetically Signal Name CCLKDS CCLKUS GPIO_00 GPIO_01 GPIO_02 GPIO_03 GPIO_04 GPIO_05 GPIO_06 GPIO_07 GPIO_11 JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N MSMBADDR_1 MSMBADDR_2 MSMBADDR_3 MSMBADDR_4 MSMBCLK MSMBDAT MSMBSMODE No Connection PE0RN00 PE0RN01 PE0RN02 I/O Type Location I A17 I C16 I/O E15 ...
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... IDT 89HPES12T3G2 Data Sheet Signal Name PE0RN03 PE0RP00 PE0RP01 PE0RP02 PE0RP03 PE0TN00 PE0TN01 PE0TN02 PE0TN03 PE0TP00 PE0TP01 PE0TP02 PE0TP03 PE2RN00 PE2RN01 PE2RN02 PE2RN03 PE2RP00 PE2RP01 PE2RP02 PE2RP03 PE2TN00 PE2TN01 PE2TN02 PE2TN03 PE2TP00 PE2TP01 PE2TP02 PE2TP03 PE4RN00 PE4RN01 PE4RN02 PE4RN03 PE4RP00 PE4RP01 ...
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... IDT 89HPES12T3G2 Data Sheet Signal Name PE4RP03 PE4TN00 PE4TN01 PE4TN02 PE4TN03 PE4TP00 PE4TP01 PE4TP02 PE4TP03 PEREFCLKN0 PEREFCLKP0 PERSTN REFCLKM REFRES0 REFRES2 REFRES4 RSTHALT SSMBADDR_1 SSMBADDR_2 SSMBADDR_3 SSMBADDR_5 SSMBCLK SSMBDAT SWMODE_0 SWMODE_1 SWMODE_2 V CORE PEA, V PEHA PETA I/O Type ...
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... IDT 89HPES12T3G2 Data Sheet PES12T3G2 Pinout — Top View Core (Power I/O (Power) DD Vss (Ground PETA (Transmitter Power) ...
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... IDT 89HPES12T3G2 Data Sheet PES12T3G2 Package Drawing — 324-Pin BC324/BCG324 March 27, 2008 ...
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... IDT 89HPES12T3G2 Data Sheet PES12T3G2 Package Drawing — Page Two March 27, 2008 ...
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... IDT 89HPES12T3G2 Data Sheet Revision History March 27, 2008: Initial publication of final data sheet March 27, 2008 ...
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... IDT 89HPES12T3G2 Data Sheet Ordering Information NN A AAA NNAN Product Operating Device Product Family Family Voltage Detail Valid Combinations 89HPES12T3G2ZABC 324-ball BGA package, Commercial Temperature 89HPES12T3G2ZABCG 324-ball Green BGA package, Commercial Temperature CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 ® ...